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11. 发明授权

US07161852B2 Semiconductor memory device with stable internal power supply voltage 有权
标题翻译：半导体存储器件具有稳定的内部电源电压
公开(公告)号：US07161852B2
公开(公告)日：2007-01-09
申请号：US11020220
申请日：2004-12-27
申请人： Seung-Wook Kwack , Kwan-Weon Kim
发明人： Seung-Wook Kwack , Kwan-Weon Kim
IPC分类号： G11C11/4074
CPC分类号： G11C11/4074 , G11C5/14 , G11C8/10
摘要： A semiconductor memory device having a register for stably generating an internal power supply voltage, including: a pumping circuit unit for generating the internal power supply voltage and adjusting a voltage level of the internal power supply voltage in response to a control signal; and a decoding unit for generating the control signal based on a plurality of address signals of the register.
摘要翻译：一种具有用于稳定地产生内部电源电压的寄存器的半导体存储器件，包括：泵电路单元，用于响应于控制信号产生内部电源电压和调节内部电源电压的电压电平; 以及解码单元，用于基于寄存器的多个地址信号产生控制信号。

12. 发明授权

US07038957B2 Semiconductor memory device for testifying over-driving quantity depending on position 失效
标题翻译：半导体存储器件，用于根据位置证明过驱动量
公开(公告)号：US07038957B2
公开(公告)日：2006-05-02
申请号：US11022803
申请日：2004-12-28
申请人： Seung-Wook Kwack , Kwan-Weon Kim
发明人： Seung-Wook Kwack , Kwan-Weon Kim
IPC分类号： G11C7/00
CPC分类号： G11C29/12005 , G11C29/12
摘要： A semiconductor memory device is capable of testifying over-driving quantity depending on position. A semiconductor memory device includes a plurality of in-bank over-drivers for temporarily applying a high voltage to a normal power that is supplied to a memory array cell within a bank; a plurality of out-bank over-drivers arranged outside the bank for temporarily applying the high voltage to the normal power that is supplied to the bank; a plurality of PERI over-drivers arranged at the peripheral area for temporarily applying the high voltage to the normal power; a mode register set for receiving a signal to select one of the over-drivers; and a decoder activated in response to a test mode signal for decoding the set value of the MRS to selectively drive the over-driver arranged at a desired position and having desired driving power among the in-bank and out-bank over-drivers and the PERI over-drivers.
摘要翻译：半导体存储器件能够根据位置来证明过驱动量。半导体存储器件包括多个行内过驱动器，用于将高电压临时施加到提供给存储体内的存储器阵列单元的正常功率; 布置在银行外部的多个外行过驱动器，用于将高电压暂时施加到提供给银行的正常电力; 多个PERI过驱动器，布置在周边区域，用于将高电压暂时施加到正常功率; 模式寄存器，用于接收信号以选择所述过驱动器之一; 以及响应于用于解码MRS的设定值的测试模式信号而激活的解码器，以选择性地驱动布置在期望位置的过驱动器并且具有期望的行内和过库驱动器之间的驱动力，并且 PERI过度司机。

13. 发明授权

US06504774B2 DDR SDRAM for stable read operation 有权
标题翻译： DDR SDRAM用于稳定的读取操作
公开(公告)号：US06504774B2
公开(公告)日：2003-01-07
申请号：US09742815
申请日：2000-12-19
申请人： Young-Jin Yoon , Kwan-Weon Kim
发明人： Young-Jin Yoon , Kwan-Weon Kim
IPC分类号： G11C1300
CPC分类号： G11C7/1066 , G11C7/1048 , G11C11/4076 , G11C11/4096
摘要： A synchronous memory device which comprises global I/O lines for data input and output from and to a memory core and a pipeline latch circuit for latching data from the global I/O lines. The synchronous memory device includes a circuit that precharges the global I/O lines when a read command signal interrupts a write operation signal, and disables the pipeline latch circuit in order to prevent write data on the global I/O lines from being latched in the pipeline latch circuit. Accordingly, the write data is prevented from being transferred to the pipeline latch circuit at an early stage of the read operation.
摘要翻译：一种同步存储器件，其包括用于数据输入和从存储器核心输出的全局I / O线以及用于锁存来自全局I / O线的数据的流水线锁存电路。同步存储装置包括当读命令信号中断写操作信号时预充电全局I / O线的电路，并且禁止流水线锁存电路以防止全局I / O线上的写数据被锁存在流水线锁存电路。因此，在读取操作的早期阶段，防止写入数据被传送到流水线锁存电路。

14. 发明授权

US07567093B2 Semiconductor memory device with on-die termination circuit 有权
标题翻译：具有片上终端电路的半导体存储器件
公开(公告)号：US07567093B2
公开(公告)日：2009-07-28
申请号：US11819800
申请日：2007-06-29
申请人： Kwan-Weon Kim , Jeong-Woo Lee
发明人： Kwan-Weon Kim , Jeong-Woo Lee
IPC分类号： H03K17/16
CPC分类号： H04L25/0278 , H03K19/017545 , H03K19/017581 , H04L25/028
摘要： A semiconductor memory device is able to inactivate an on-die termination circuit without an additional pin. The semiconductor memory device includes a control signal generator, a resistance control unit, and a resistance supply unit. The control signal generator generates an initializing signal and driving clocks in response to a plurality of control signals. The resistance control unit, initialized by the initializing signal, generates a termination-off signal in response to the driving clocks. The resistance supply unit supplies termination resistance in response to the termination-off signal and a mode register setting value. The plurality of control signals are inputted through input pins not connected to the resistance supply unit.
摘要翻译：半导体存储器件能够在没有附加引脚的情况下使管芯端接电路失活。半导体存储器件包括控制信号发生器，电阻控制单元和电阻供应单元。控制信号发生器响应于多个控制信号产生初始化信号和驱动时钟。由初始化信号初始化的电阻控制单元响应于驱动时钟产生终止关闭信号。电阻供应单元响应于终止信号和模式寄存器设置值提供终止电阻。多个控制信号通过未连接到电阻供应单元的输入引脚输入。

15. 发明授权

US07427935B2 Apparatus and method of generating reference voltage of semiconductor integrated circuit 有权
标题翻译：生成半导体集成电路参考电压的装置和方法
公开(公告)号：US07427935B2
公开(公告)日：2008-09-23
申请号：US11647482
申请日：2006-12-29
申请人： Kwan-Weon Kim
发明人： Kwan-Weon Kim
IPC分类号： H03M1/10
CPC分类号： G11C5/143
摘要： An apparatus for generating a reference voltage of a semiconductor integrated circuit includes a resistance control unit that adjusts at least one an adjustment code such that at least one set of resistors, which have resistances determined according to the at least one adjustment code have predetermined resistances, a voltage level control unit that generates a selection code for selecting the level of a final reference voltage under external control and outputs the generated selection code, and a reference voltage generating unit that converts a power supply voltage according to the adjustment code and the selection code and outputs the final reference voltage.
摘要翻译：一种用于产生半导体集成电路的参考电压的装置包括：电阻控制单元，其调整至少一个调整代码，使得至少一组具有根据至少一个调整代码确定的电阻的电阻器具有预定电阻，电压电平控制单元，其生成用于选择外部控制下的最终参考电压的电平的选择码，并输出所生成的选择码;以及参考电压生成单元，其根据调整码和选择码转换电源电压并输出最终参考电压。

16. 发明申请

US20060023522A1 Semiconductor memory device with stable internal power supply voltage 有权
标题翻译：半导体存储器件具有稳定的内部电源电压
公开(公告)号：US20060023522A1
公开(公告)日：2006-02-02
申请号：US11020220
申请日：2004-12-27
申请人： Seung-Wook Kwack , Kwan-Weon Kim
发明人： Seung-Wook Kwack , Kwan-Weon Kim
IPC分类号： G11C7/00
CPC分类号： G11C11/4074 , G11C5/14 , G11C8/10
摘要： A semiconductor memory device having a register for stably generating an internal power supply voltage, including: a pumping circuit unit for generating the internal power supply voltage and adjusting a voltage level of the internal power supply voltage in response to a control signal; and a decoding unit for generating the control signal based on a plurality of address signals of the register.
摘要翻译：一种具有用于稳定地产生内部电源电压的寄存器的半导体存储器件，包括：泵电路单元，用于响应于控制信号产生内部电源电压和调节内部电源电压的电压电平; 以及解码单元，用于基于寄存器的多个地址信号产生控制信号。

17. 发明申请

US20050111268A1 Semiconductor memory device to supply stable high voltage during auto-refresh operation and method therefor 有权
标题翻译：在自动刷新操作期间提供稳定的高电压的半导体存储器件及其方法
公开(公告)号：US20050111268A1
公开(公告)日：2005-05-26
申请号：US10881434
申请日：2004-06-29
申请人： Kwan-Weon Kim
发明人： Kwan-Weon Kim
IPC分类号： G11C11/407 , G11C5/14 , G11C7/00 , G11C11/403 , G11C11/406 , G11C11/4074
CPC分类号： G11C11/40611 , G11C11/406 , G11C11/4074
摘要： A semiconductor device for use in a semiconductor memory device for pumping a supplying voltage according to a data access mode and an auto-refresh mode, including: a voltage level detecting means for generating a voltage level detect signal by detecting a voltage level of the supplying voltage; an auto-refresh signal detecting means for generating an auto-refresh detect signal in response to an auto-refresh signal; and a voltage pumping means for pumping the supplying voltage in response to the voltage level detect signal at the data access mode or in response to the auto-refresh detect signal at the auto-refresh mode.
摘要翻译：一种用于半导体存储器件的半导体器件，用于根据数据存取模式和自动刷新模式对供电电压进行泵浦，包括：电压电平检测装置，用于通过检测供电电压的电压电平来产生电压电平检测信号电压; 自动刷新信号检测装置，用于响应于自动刷新信号产生自动刷新检测信号; 以及用于在数据访问模式下响应于电压电平检测信号或响应于自动刷新模式下的自动刷新检测信号来泵送供电电压的电压泵送装置。

18. 发明授权

US06288971B1 Apparatus for generating data strobe signal applicable to double data rate SDRAM 有权
标题翻译：用于产生数据选通信号的装置适用于双倍数据速率SDRAM
公开(公告)号：US06288971B1
公开(公告)日：2001-09-11
申请号：US09603912
申请日：2000-06-26
申请人： Kwan-Weon Kim
发明人： Kwan-Weon Kim
IPC分类号： G11C800
CPC分类号： G11C7/1066 , G11C7/1072 , G11C7/22 , G11C11/4076
摘要： A synchronous memory device having an apparatus for generating a data strobe signal, the apparatus for generating a data strobe signal includes: a preamble control unit for controlling a preamble state of a data strobe signal in response to a data strobe preamble control signal; at least one pair of pull-up/pull-down signal generating unit coupled to the preamble control unit, for receiving pipe counter signals at a first input terminal to generate pull-up and pull-down signals; a common pull-up signal buffering unit for buffering the pull-up signal to generate a buffered pull-up signal, wherein the buffered pull-up signal is commonly inputted to a second input terminal of the pull-up/pull-down signal generating unit; a common pull-down signal buffering unit for buffering the pull-up signal to generate a buffered pull-down signal, wherein the buffered pull-down signal is commonly inputted to a third input terminal of the pull-up/pull-down signal generating unit; and a data strobe signal driving unit for outputting the data strobe signal in response to the pull-up signal, the pull-down signals and a data strobe enable signal.
摘要翻译：一种具有用于产生数据选通信号的装置的同步存储装置，用于产生数据选通信号的装置包括：前导码控制单元，用于响应于数据选通前导码控制信号控制数据选通信号的前导码状态; 耦合到前置码控制单元的至少一对上拉/下拉信号生成单元，用于在第一输入端子处接收管道计数器信号以产生上拉和下拉信号; 用于缓冲上拉信号以产生缓冲上拉信号的公共上拉信号缓冲单元，其中缓冲上拉信号通常被输入到产生上拉/下拉信号的第二输入端单元; 公共下拉信号缓冲单元，用于缓冲上拉信号以产生缓冲的下拉信号，其中缓冲下拉信号通常输入到上拉/下拉信号产生的第三输入端单元; 以及数据选通信号驱动单元，用于响应于上拉信号，下拉信号和数据选通使能信号输出数据选通信号。

19. 发明申请

US20100290302A1 FUSE CIRCUIT AND DRIVING METHOD THEREOF 有权
标题翻译：保险丝电路及其驱动方法
公开(公告)号：US20100290302A1
公开(公告)日：2010-11-18
申请号：US12494616
申请日：2009-06-30
申请人： Keun-Soo Song , Kwan-Weon Kim
发明人： Keun-Soo Song , Kwan-Weon Kim
IPC分类号： G11C17/18 , H01H37/76
CPC分类号： G11C29/785 , G11C17/18 , G11C29/02 , G11C29/027
摘要： A fuse circuit includes a fuse unit configured to form a current path on a first node according to whether or not a fuse is cut; a driving current controller configured to control a potential level of the first node in response to a test signal; and an output unit configured to output a fuse state signal in response to the potential level of the first node.
摘要翻译：保险丝电路包括：熔丝单元，被配置为根据是否切断熔丝形成第一节点上的电流路径; 驱动电流控制器，被配置为响应于测试信号来控制所述第一节点的电位电平; 以及输出单元，被配置为响应于第一节点的电位电平输出熔丝状态信号。

20. 发明申请

US20060012419A1 Input stage circuit of semiconductor device 审中-公开
标题翻译：半导体器件的输入级电路
公开(公告)号：US20060012419A1
公开(公告)日：2006-01-19
申请号：US11020246
申请日：2004-12-27
申请人： Kwan-Weon Kim
发明人： Kwan-Weon Kim
IPC分类号： H03B1/00
CPC分类号： H03K5/08
摘要： Disclosed is an input stage circuit of a semiconductor device which is effective for preventing a reference voltage fluctuation. The input stage circuit of the semiconductor memory device includes: a reference voltage input pin connected to an external reference voltage terminal, wherein the reference voltage is used for determining a digital value; a reference voltage line for applying the reference voltage from the reference voltage input pin; a first drive voltage line for applying a first drive voltage into the semiconductor device; a second drive voltage line for applying a second drive voltage into the semiconductor device; a first coupler for coupling the reference voltage line with the first drive voltage line; and a second coupler for coupling the reference voltage line with the second drive voltage line.
摘要翻译：公开了半导体器件的输入级电路，其有效地防止参考电压波动。半导体存储器件的输入级电路包括：连接到外部参考电压端子的参考电压输入引脚，其中参考电压用于确定数字值; 用于从参考电压输入引脚施加参考电压的参考电压线; 用于将第一驱动电压施加到所述半导体器件中的第一驱动电压线; 用于将第二驱动电压施加到所述半导体器件中的第二驱动电压线; 用于将参考电压线与第一驱动电压线耦合的第一耦合器; 以及用于将参考电压线与第二驱动电压线耦合的第二耦合器。

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