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11. 发明申请

US20070222020A1 DRAM (DYNAMIC RANDOM ACCESS MEMORY) CELLS 失效
标题翻译： DRAM（动态随机存取存储器）电池
公开(公告)号：US20070222020A1
公开(公告)日：2007-09-27
申请号：US11308404
申请日：2006-03-22
申请人： Kangguo Cheng , Babar Khan
发明人： Kangguo Cheng , Babar Khan
IPC分类号： H01L29/00
CPC分类号： H01L27/1087
摘要： A DRAM cell with a self-aligned gradient P-well and a method for forming the same. The DRAM cell includes (a) a semiconductor substrate; (b) an electrically conducting region including a first portion, a second portion, and a third portion; (c) a first doped semiconductor region wrapping around the first portion, but electrically insulated from the first portion by a capacitor dielectric layer; (d) a second doped semiconductor region wrapping around the second portion, but electrically insulated from the second portion by a collar dielectric layer. The second portion is on top of and electrically coupled to the first portion, and the third portion is on top of and electrically coupled to the second portion. The collar dielectric layer is in direct physical contact with the capacitor dielectric layer. When going away from the collar dielectric layer, a doping concentration of the second doped semiconductor region decreases.
摘要翻译：具有自对准梯度P阱的DRAM单元及其形成方法。 DRAM单元包括（a）半导体衬底; （b）包括第一部分，第二部分和第三部分的导电区域; （c）围绕所述第一部分包围但与所述第一部分由电容器介电层电绝缘的第一掺杂半导体区域; （d）围绕第二部分缠绕的第二掺杂半导体区域，但是通过套环电介质层与第二部分电绝缘。第二部分在第一部分的顶部并且电耦合到第一部分，并且第三部分在第二部分的顶部并且电耦合到第二部分。套环电介质层与电容器电介质层直接物理接触。当离开套环电介质层时，第二掺杂半导体区域的掺杂浓度降低。

12. 发明申请

US20060163636A1 TRENCH CAPACITOR ARRAY HAVING WELL CONTACTING MERGED PLATE 失效
标题翻译： TRENCH电容阵列具有良好的接触合并板
公开(公告)号：US20060163636A1
公开(公告)日：2006-07-27
申请号：US10905808
申请日：2005-01-21
申请人： Kangguo Cheng , Babar Khan , Carl Radens
发明人： Kangguo Cheng , Babar Khan , Carl Radens
IPC分类号： H01L29/94
CPC分类号： H01L29/945
摘要： According to an aspect of the invention, a structure is provided in which an array of trench capacitors includes a well contact to a merged buried plate diffusion region. The array, which is disposed in a substrate, includes a contact for receiving a reference potential. Each trench capacitor includes a node dielectric and a node conductor formed within the trench. Buried plate (BP) diffusions extend laterally outward from a lower portion of each trench of the array, the BP diffusions merging to form an at least substantially continuous BP diffusion region across the array. An isolation region extends over a portion of the BP diffusion region. A doped well region is formed within the substrate extending from a major surface of the substrate to a depth below a top level of the substantially continuous BP diffusion region. An electrical interconnection is also provided to the well region.
摘要翻译：根据本发明的一个方面，提供了一种结构，其中沟槽电容器阵列包括与合并的掩埋板扩散区的阱接触。布置在基板中的阵列包括用于接收参考电位的触点。每个沟槽电容器包括形成在沟槽内的节点电介质和节点导体。掩埋板（BP）扩散从阵列的每个沟槽的下部横向向外延伸，BP扩散合并以在阵列上形成至少基本上连续的BP扩散区域。隔离区域在BP扩散区域的一部分上延伸。在衬底内形成掺杂阱区，该衬底从衬底的主表面延伸至低于基本上连续的BP扩散区的顶层的深度。还向阱区域提供电互连。

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