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11. 发明授权

US06724361B1 Shift register and image display device 有权
标题翻译：移位寄存器和图像显示设备
公开(公告)号：US06724361B1
公开(公告)日：2004-04-20
申请号：US09703918
申请日：2000-11-01
申请人： Hajime Washio , Yasushi Kubota , Kazuhiro Maeda , Yasuyoshi Kaise , Michael James Brownlow , Graham Andrew Cairns
发明人： Hajime Washio , Yasushi Kubota , Kazuhiro Maeda , Yasuyoshi Kaise , Michael James Brownlow , Graham Andrew Cairns
IPC分类号： G09G336
CPC分类号： G09G3/3677 , G09G3/3688 , G09G2310/0289
摘要： In a shift register provided with flip-flops that operate in synchronism with a clock signal, and a switching means, which is opened and closed in response to an output of the preceding stage of each of the flip-flops, is installed. The clock signal is selectively inputted by the switching means, and the selected clock signal is inverted and used as a shift register output from each of the stages. An output pulse having the same width as the pulse of the clock signal is generated.
摘要翻译：在设置有与时钟信号同步工作的触发器的移位寄存器中，并且响应于每个触发器的前级的输出而被打开和关闭的开关装置被安装。时钟信号由切换装置选择性地输入，所选择的时钟信号被反相并用作从每个级输出的移位寄存器。产生具有与时钟信号的脉冲相同宽度的输出脉冲。

12. 发明授权

US07339570B2 Data signal line drive circuit, drive circuit, image display device incorporating the same, and electronic apparatus using the same 有权
标题翻译：数据信号线驱动电路，驱动电路，并入其的图像显示装置，以及使用该数据信号线的电子装置
公开(公告)号：US07339570B2
公开(公告)日：2008-03-04
申请号：US09851885
申请日：2001-05-09
申请人： Yasushi Kubota , Hajime Washio , Michael James Brownlow , Graham Andrew Cairns , Yasuyoshi Kaise , Kazuhiro Maeda
发明人： Yasushi Kubota , Hajime Washio , Michael James Brownlow , Graham Andrew Cairns , Yasuyoshi Kaise , Kazuhiro Maeda
IPC分类号： G09G3/36
CPC分类号： G09G3/2011 , G09G3/3648 , G09G3/3677 , G09G3/3688 , G09G5/005 , G09G5/006 , G09G2300/0456 , G09G2310/0205 , G09G2310/0248 , G09G2310/027 , G09G2310/0281 , G09G2310/0289 , G09G2310/0294 , G09G2320/0626 , G09G2330/021 , G09G2340/0428 , G09G2340/10 , G09G2340/12 , G09G2360/144 , H01L27/124 , H04N2007/145
摘要： An image display device includes two data signal line drive circuits and two scan signal line drive circuits configured differently from each other. Different data signal line drive circuits and scan signal line drive circuit are compatible with different display formats. A display can be produced in the most suitable display format, and power consumption also can be reduced, by switch operating drive circuits according to the kind of input video and environmental conditions. Further, an image can be written over another image by writing video signals to signal lines with a time lag using a plurality of drive circuits; therefore, a superimposed display can be produced without externally processing the video signals. Thus, both a satisfactory image display and low power consumption can be achieved in an image display device.
摘要翻译：图像显示装置包括两个数据信号线驱动电路和彼此不同地配置的两个扫描信号线驱动电路。不同的数据信号线驱动电路和扫描信号线驱动电路兼容不同的显示格式。可以以最合适的显示格式生产显示器，并且可以通过根据输入视频的类型和环境条件的开关操作驱动电路来降低功耗。此外，通过使用多个驱动电路将视频信号以时间滞后的方式写入信号线，可以在另一图像上写入图像; 因此，可以在不外部处理视频信号的情况下产生叠加显示。因此，可以在图像显示装置中实现令人满意的图像显示和低功耗。

13. 发明授权

US06909417B2 Shift register and image display apparatus using the same 有权
标题翻译：移位寄存器和使用其的图像显示装置
公开(公告)号：US06909417B2
公开(公告)日：2005-06-21
申请号：US09578440
申请日：2000-05-25
申请人： Hajime Washio , Yasushi Kubota , Kazuhiro Maeda , Yasuyoshi Kaise , Michael James Brownlow , Graham Andrew Cairns
发明人： Hajime Washio , Yasushi Kubota , Kazuhiro Maeda , Yasuyoshi Kaise , Michael James Brownlow , Graham Andrew Cairns
IPC分类号： G11C19/00 , G09G3/20 , G09G3/36
CPC分类号： G09G3/3688 , G09G2300/0408 , G09G2310/0289 , G09G2330/021
摘要： A level shifter 13 is provided for each of SR flip flops F1 constituting a shift register 11. The level shifter 13 increases a voltage of a clock signal CK. This arrangement reduces a distance for transmitting a clock signal whose voltage has been increased, as compared with a construction in which a voltage of a clock signal is increased by a single level shifter and the signal is transmitted to each of the flip flops; consequently, a load capacity of the level shifter can be smaller. Furthermore, each of the level shifters is operated during a pulse output of the previous level shifter 13, and the operation is suspended at the end of the pulse output. Thus, the level shifters 13 can operate only when it is necessary to apply a clock signal CK to the corresponding SR flip flop F1. As a result, even when an amplitude of a clock signal is small, it is possible to reduce power consumption of the shift resister under normal operation.
摘要翻译：为构成移位寄存器11的每个SR触发器F 1提供电平移位器13.电平移位器13增加时钟信号CK的电压。与通过单个电平移位器增加时钟信号的电压并且将信号发送到每个触发器的结构相比，这种布置减少了用于传输电压已经增加的时钟信号的距离; 因此，电平转换器的负载能力可以更小。此外，每个电平移位器在先前电平移位器13的脉冲输出期间操作，并且在脉冲输出结束时暂停操作。因此，只有当需要对相应的SR触发器F 1施加时钟信号CK时，电平移位器13才能够工作。结果，即使当时钟信号的幅度小时，也可以降低功耗的正常运行中的移位寄存器。

14. 发明授权

US08130216B2 Display device having display area and non-display area, and driving method thereof 有权
标题翻译：具有显示区域和非显示区域的显示装置及其驱动方法
公开(公告)号：US08130216B2
公开(公告)日：2012-03-06
申请号：US11882533
申请日：2007-08-02
申请人： Hajime Washio , Yasuyoshi Kaise , Sachio Tsujino , Kazuhiro Maeda , Keiji Takahashi , Yasushi Kubota , Toshiya Aoki
发明人： Hajime Washio , Yasuyoshi Kaise , Sachio Tsujino , Kazuhiro Maeda , Keiji Takahashi , Yasushi Kubota , Toshiya Aoki
IPC分类号： G09G5/00
CPC分类号： G09G3/3688 , G09G3/3614 , G09G3/3648 , G09G3/3666 , G09G3/3677 , G09G2310/0213 , G09G2310/0232 , G09G2310/027 , G09G2310/0283 , G09G2310/0297 , G09G2310/04 , G09G2320/0214 , G09G2320/10 , G09G2330/021
摘要： An example control signal generating circuit CTL for controlling the writing into pixels PIX instructs a data signal line drive circuit SD2, which is for driving pixels in a non-display area, to write a voltage VB or a voltage VW which are for non-displaying, not only in the first frame but also once in a predetermined number of frames. In other words, the pixels in the display area are refreshed at intervals longer than those in the case of refreshing the pixels in each frame. Thus, even if the mobility of an active element is high and the leak current on the occasion of OFF-state is large, or even if a large amount of electric charge is accumulated because of the photoelectric effect due to the use of a backlight, it is possible to prevent unnecessary displaying on the display area, which is caused because the writing into the pixels in the display area influences on the pixels in the non-display area, and hence it is possible to improve the quality of partial displaying, while restraining the power consumption.
摘要翻译：用于控制写入像素PIX的示例性控制信号发生电路CTL指示用于驱动非显示区域中的像素的数据信号线驱动电路SD2写入用于不显示的电压VB或电压VW ，不仅在第一帧中，而且在预定数量的帧中也是一次。换句话说，显示区域中的像素以比刷新每帧中的像素的情况更长的间隔更新。因此，即使有源元件的迁移率高，关断状态下的漏电流大，或者即使由于使用背光导致的光电效应而累积大量的电荷，可以防止由于对显示区域中的像素的写入而影响非显示区域中的像素而导致的显示区域的不必要的显示，因此可以提高部分显示的质量，同时限制功耗。

15. 发明授权

US07460099B2 Latch circuit, shift register circuit, logical circuit and image display device operated with a low consumption of power 有权
标题翻译：锁存电路，移位寄存器电路，逻辑电路和图像显示设备以低功耗运行
公开(公告)号：US07460099B2
公开(公告)日：2008-12-02
申请号：US10949990
申请日：2004-09-23
申请人： Yasushi Kubota , Hajime Washio , Ichiro Shiraki , Kazuhiro Maeda , Yasuyoshi Kaise
发明人： Yasushi Kubota , Hajime Washio , Ichiro Shiraki , Kazuhiro Maeda , Yasuyoshi Kaise
IPC分类号： G09G3/36 , G09G5/00
CPC分类号： G09G3/3677 , G09G3/3688 , G09G2300/0408 , G09G2300/0417 , G09G2310/021 , G09G2310/0289 , G09G2330/021 , G11C19/00 , G11C19/28
摘要： A CMOS logical circuit comprises two electric current paths each of which has circuits consisting of n-type and p-type transistors. In a circuit consisting of n-type or p-type transistors, one electric current path is provided with a circuit having the same construction as that of a circuit having an n-type transistor of a CMOS logical circuit outputting a logical operation result similar to that of this logical circuit, and the other electric current path is provided with a circuit having the same construction as that of a circuit having a p-type transistor of the CMOS logical circuit outputting a logical operation result similar to that of this logical circuit. In another circuit consisting of the other channel type, a gate electrode of the transistor provided on the one electric current path and that of the transistor provided on the other electric current path are connected to drain electrodes of the counterparts. According to the construction, the amplitude of an input signal can be made smaller than a supply voltage of the logical circuit.
摘要翻译： CMOS逻辑电路包括两个电流路径，每个电路具有由n型和p型晶体管组成的电路。在由n型或p型晶体管组成的电路中，一个电流路径设置有与具有CMOS逻辑电路的n型晶体管的电路相同结构的电路，该逻辑电路输出类似于该逻辑电路的另一个电流路径具有与具有CMOS逻辑电路的p型晶体管的电路相同结构的电路，该电路输出类似于该逻辑电路的逻辑运算结果。在由另一沟道型构成的另一电路中，设置在一个电流路径上的晶体管的栅电极和设置在另一电流路径上的晶体管的栅电极连接到对应物的漏电极。根据该结构，可以使输入信号的幅度小于逻辑电路的电源电压。

16. 发明授权

US07333096B2 Display device and driving method thereof 有权
标题翻译：显示装置及其驱动方法
公开(公告)号：US07333096B2
公开(公告)日：2008-02-19
申请号：US10316193
申请日：2002-12-11
申请人： Hajime Washio , Yasuyoshi Kaise , Sachio Tsujino , Kazuhiro Maeda , Keiji Takahashi , Yasushi Kubota , Toshiya Aoki
发明人： Hajime Washio , Yasuyoshi Kaise , Sachio Tsujino , Kazuhiro Maeda , Keiji Takahashi , Yasushi Kubota , Toshiya Aoki
IPC分类号： G09G5/00 , G09G3/36
CPC分类号： G09G3/3688 , G09G3/3614 , G09G3/3648 , G09G3/3666 , G09G3/3677 , G09G2310/0213 , G09G2310/0232 , G09G2310/027 , G09G2310/0283 , G09G2310/0297 , G09G2310/04 , G09G2320/0214 , G09G2320/10 , G09G2330/021
摘要： A control signal generating circuit CTL for controlling the writing into pixels PIX instructs a data signal line drive circuit SD2, which is for driving pixels in a non-display area, to write a voltage VB or a voltage VW which are for non-displaying, not only in the first frame but also once in a predetermined number of frames. In other words, the pixels in the display area is refreshed at intervals longer than those in the case of refreshing the pixels in each frame. Thus, even if the mobility of an active element is high and the leak current on the occasion of OFF-state is large, or even if a large amount of electric charge is accumulated because of the photoelectric effect due to the use of a backlight, it is possible to prevent unnecessary displaying on the display area, which is caused because the writing into the pixels in the display area influences on the pixels in the non-display area, and hence it is possible to improve the quality of partial displaying, while restraining the power consumption.
摘要翻译：用于控制向像素PIX写入的控制信号发生电路CTL指示用于驱动非显示区域中的像素的数据信号线驱动电路SD 2写入用于不显示的电压VB或电压VW ，不仅在第一帧中，而且在预定数量的帧中也是一次。换句话说，显示区域中的像素以比刷新每帧中的像素的情况更长的间隔更新。因此，即使有源元件的迁移率高，关断状态下的漏电流大，或者即使由于使用背光导致的光电效应而累积大量的电荷，可以防止由于对显示区域中的像素的写入而影响非显示区域中的像素而导致的显示区域的不必要的显示，因此可以提高部分显示的质量，同时限制功耗。

17. 发明授权

US07212184B2 Shift register and image display device 有权
标题翻译：移位寄存器和图像显示设备
公开(公告)号：US07212184B2
公开(公告)日：2007-05-01
申请号：US10800352
申请日：2004-03-12
申请人： Hajime Washio , Yasushi Kubota , Kazuhiro Maeda , Yasuyoshi Kaise , Michael James Brownlow , Graham Andrew Cairns
发明人： Hajime Washio , Yasushi Kubota , Kazuhiro Maeda , Yasuyoshi Kaise , Michael James Brownlow , Graham Andrew Cairns
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G09G3/3688 , G09G2310/0289
摘要： In a shift register provided with flip-flops that operate in synchronism with a clock signal, and a switching means, which is opened and closed in response to an output of the preceding stage of each of the flip-flops, is installed. The clock signal is selectively inputted by the switching means, and the selected clock signal is inverted and used as a shift register output from each of the stages. Moreover, two kinds of clock signals, each of which has a duty ratio of not more than 50% and which have no overlapped portions in their low-level periods, are used so as to prevent the outputs of the shift-register from overlapping each other. Thus, it is possible to provide a shift register which is preferably used for a driving circuit of an image display device, can miniaturize the driving circuit, and can desirably change the pulse width of the output signal, and also to provide an image display device using such a shift register.
摘要翻译：在设置有与时钟信号同步工作的触发器的移位寄存器中，并且响应于每个触发器的前级的输出而被打开和关闭的开关装置被安装。时钟信号由切换装置选择性地输入，所选择的时钟信号被反相并用作从每个级输出的移位寄存器。此外，使用两种时钟信号，每个时钟信号的占空比不大于50％，并且在其低电平时段中没有重叠部分，以便防止移位寄存器的输出与每个其他。因此，可以提供优选用于图像显示装置的驱动电路的移位寄存器，可以使驱动电路小型化，并且可以期望地改变输出信号的脉冲宽度，并且还提供图像显示装置使用这种移位寄存器。

18. 发明授权

US07190338B2 Data signal line drive circuit, drive circuit, image display device incorporating the same, and electronic apparatus using the same 有权
标题翻译：数据信号线驱动电路，驱动电路，并入其的图像显示装置，以及使用该数据信号线的电子装置
公开(公告)号：US07190338B2
公开(公告)日：2007-03-13
申请号：US11091012
申请日：2005-03-25
申请人： Yasushi Kubota , Hajime Washio , Michael James Brownlow , Graham Andrew Cairns , Yasuyoshi Kaise , Kazuhiro Maeda
发明人： Yasushi Kubota , Hajime Washio , Michael James Brownlow , Graham Andrew Cairns , Yasuyoshi Kaise , Kazuhiro Maeda
IPC分类号： G09G5/00
CPC分类号： G09G3/2011 , G09G3/3648 , G09G3/3677 , G09G3/3688 , G09G5/005 , G09G5/006 , G09G2300/0456 , G09G2310/0205 , G09G2310/0248 , G09G2310/027 , G09G2310/0281 , G09G2310/0289 , G09G2310/0294 , G09G2320/0626 , G09G2330/021 , G09G2340/0428 , G09G2340/10 , G09G2340/12 , G09G2360/144 , H01L27/124 , H04N2007/145
摘要： An image display device includes two data signal line drive circuits and two scan signal line drive circuits configured differently from each other. Different data signal line drive circuits and scan signal line drive circuit are compatible with different display formats. A display can be produced in the most suitable display format, and power consumption also can be reduced, by switch operating drive circuits according to the kind of input video and environmental conditions. Further, an image can be written over another image by writing video signals to signal lines with a time lag using a plurality of drive circuits; therefore, a superimposed display can be produced without externally processing the video signals. Thus, both a satisfactory image display and low power consumption can be achieved in an image display device.
摘要翻译：图像显示装置包括两个数据信号线驱动电路和彼此不同地配置的两个扫描信号线驱动电路。不同的数据信号线驱动电路和扫描信号线驱动电路兼容不同的显示格式。可以以最合适的显示格式生产显示器，并且可以通过根据输入视频的类型和环境条件的开关操作驱动电路来降低功耗。此外，通过使用多个驱动电路将视频信号以时间滞后的方式写入信号线，可以在另一图像上写入图像; 因此，可以在不外部处理视频信号的情况下产生叠加显示。因此，可以在图像显示装置中实现令人满意的图像显示和低功耗。

19. 发明授权

US06836269B2 Precharge circuit and image display device using the same 有权
标题翻译：预充电电路和使用其的图像显示装置
公开(公告)号：US06836269B2
公开(公告)日：2004-12-28
申请号：US09795658
申请日：2001-02-28
申请人： Kazuhiro Maeda , Hajime Washio , Yasushi Kubota , Yasuyoshi Kaise , Michael James Brownlow , Graham Andrew Cairns
发明人： Kazuhiro Maeda , Hajime Washio , Yasushi Kubota , Yasuyoshi Kaise , Michael James Brownlow , Graham Andrew Cairns
IPC分类号： G09G500
CPC分类号： G09G3/3688 , G09G2310/0248 , G09G2310/0289 , G09G2330/021
摘要： A precharge control circuit constituted by (1) a latch circuit mounted in a precharge circuit and (2) a level shifter circuit of a current drive type controlled through an output of the latch circuit is included. The precharge control circuit changes the latch circuit to an active state to cause the level shifter circuit of a current drive type to operate only during a precharge period and also during immediately preceding and succeeding periods, and outside these periods, changes the latch circuit in a non-active state and the level shifter circuit of a current drive type in an operating state to save power consumption in the level shifter circuit. This enables a low-power-consuming precharge circuit, as well as a low-power-consuming image display device with a high quality display capability, to be offered.
摘要翻译：一种预充电控制电路，包括：（1）安装在预充电电路中的锁存电路和（2）通过锁存电路的输出控制的电流驱动型电平移位电路。预充电控制电路将锁存电路改变为有效状态，使得电流驱动类型的电平移动电路仅在预充电期间以及在紧接之前和之后周期期间操作，并且在这些周期之外，将锁存电路改变为非活动状态和电流驱动类型的电平移位器电路，以在电平移位器电路中节省功耗。这使得能够提供低功耗预充电电路以及具有高质量显示能力的低功耗图像显示装置。

20. 发明授权

US06879313B1 Shift register circuit, image display apparatus having the circuit, and driving method for LCD devices 有权
标题翻译：移位寄存器电路，具有电路的图像显示装置以及LCD装置的驱动方法
公开(公告)号：US06879313B1
公开(公告)日：2005-04-12
申请号：US09523511
申请日：2000-03-10
申请人： Yasushi Kubota , Hajime Washio , Shigeto Yoshida , Kazuhiro Maeda , Hiroshi Yoneda
发明人： Yasushi Kubota , Hajime Washio , Shigeto Yoshida , Kazuhiro Maeda , Hiroshi Yoneda
IPC分类号： G09G3/36 , G11C19/28 , G11C19/00
CPC分类号： G09G3/3688 , G09G2310/0286 , G09G2310/061 , G09G2310/08 , G09G2320/0233 , G11C19/28
摘要： A shift register circuit includes a plurality of latch circuits connected in series to sequentially transfer a pulse signal ST from one to another, a clock signal line transmitting a clock signal CLK, and a plurality of switching circuits performing electrical connection and disconnection between the clock signal line and the plurality of latch circuits. Upon turning on the shift register, at least one of the switching circuits electrically disconnects at least one of the latch circuits from the clock signal line. During an initialization period immediately after power has been turned on, the frequency of the clock signal CLK is lower than in a normal operation period and gradually increases toward the frequency used in the normal operation period.
摘要翻译：移位寄存器电路包括串联连接的多个锁存电路，以顺序地将脉冲信号ST从一个传送到另一个，一个发送时钟信号CLK的时钟信号线以及执行时钟信号之间的电连接和断开的多个开关电路线和多个锁存电路。在接通移位寄存器时，至少一个开关电路将至少一个锁存电路与时钟信号线电断开。在电源接通之后的初始化期间，时钟信号CLK的频率比正常运行期间低，并且在正常运行期间逐渐增大。

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