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11. 发明授权

US07538967B1 Method and apparatus for estimating a position of a head in a disk drive 有权
标题翻译：用于估计磁盘驱动器中磁头位置的方法和装置
公开(公告)号：US07538967B1
公开(公告)日：2009-05-26
申请号：US11765889
申请日：2007-06-20
申请人： Xueshi Yang , Michael Madden , Zining Wu
发明人： Xueshi Yang , Michael Madden , Zining Wu
IPC分类号： G11B5/596 , H04B15/00
CPC分类号： G11B5/5556 , G11B5/59611
摘要： In a method for providing an estimate of a head position for a disk drive, a readback signal is filtered. The readback signal includes a first position signal component corresponding to a first position pattern on a disk, and includes a second position signal component corresponding to a second position pattern on the disk. Filtering the readback signal enhances a signal-to-noise ratio (SNR) of the readback signal with respect to the first position signal component and the second position signal component. An estimate of an amplitude of the first position signal component is generated based on the filtered readback signal, and an estimate of an amplitude of the second position signal component is generated based on the filtered readback signal. An estimate of a head position with respect to a track on the disk is generated based on the estimate of the amplitude of the first position signal component and the estimate of the amplitude of the second position signal component.
摘要翻译：在用于提供磁盘驱动器的磁头位置的估计的方法中，滤波回读信号。回读信号包括对应于盘上的第一位置图案的第一位置信号分量，并且包括对应于盘上的第二位置图案的第二位置信号分量。过滤回读信号增强了回读信号相对于第一位置信号分量和第二位置信号分量的信噪比（SNR）。基于经滤波的回读信号生成第一位置信号分量的振幅的估计，并且基于滤波的回读信号生成第二位置信号分量的振幅的估计。基于第一位置信号分量的振幅的估计和第二位置信号分量的振幅的估计，产生相对于磁盘上的磁道的磁头位置的估计。

12. 发明申请

US20070195912A1 Low-latency baseline-wander compensation systems and methods 有权
标题翻译：低延迟基线漂移补偿系统和方法
公开(公告)号：US20070195912A1
公开(公告)日：2007-08-23
申请号：US11520531
申请日：2006-09-12
申请人： Xueshi Yang , Zining Wu
发明人： Xueshi Yang , Zining Wu
IPC分类号： H03D1/00
CPC分类号： G11B20/10296 , G11B20/10203 , H03M13/41
摘要： Disclosed herein are systems and methods for detecting a signal to provide a detected data sequence, comprising providing a plurality of candidate data sequences, computing baseline wander estimates associated with respective ones of the candidate data sequences, comparing a signal to each of the respective ones of the candidate data sequences, wherein the comparisons are compensated by corresponding ones of the baseline wander estimates, and choosing, based on the comparisons, one of the plurality of candidate data sequences to be the detected data sequence.
摘要翻译：本文公开了用于检测信号以提供检测到的数据序列的系统和方法，包括提供多个候选数据序列，计算与候选数据序列中的相应数据序列相关联的基线漂移估计，将信号与候选数据序列，其中比较由对应的基线漂移估计补偿，并且基于比较，选择多个候选数据序列中的一个作为检测数据序列。

13. 发明授权

US08817535B1 Programming method for multi-level cell flash for minimizing inter-cell interference 有权
标题翻译：用于最小化单元间干扰的多级单元闪存的编程方法
公开(公告)号：US08817535B1
公开(公告)日：2014-08-26
申请号：US13543634
申请日：2012-07-06
申请人： Xueshi Yang , Zining Wu
发明人： Xueshi Yang , Zining Wu
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C2211/5648
摘要： Systems, methods and computer program products for minimizing floating gate coupling interference and threshold voltage drift associated with flash memory cells are described. In some implementations, the memory cells can be programmed in a predetermined sequence that allows pages with the most-significant bit (MSB) and central significant bit (CSB) to be programmed first prior to programming pages with the least-significant bit (LSB). This sequence allows neighboring cells (e.g., cells neighboring a target cell) to be programmed first so as to reduce the floating gate coupling interference and threshold voltage drift on the target cell that is to be programmed in the subsequent stage. To accommodate the programming sequence (e.g., at the device level), additional buffer memories can be added.
摘要翻译：描述了用于最小化与闪存单元相关联的浮动栅极耦合干扰和阈值电压漂移的系统，方法和计算机程序产品。在一些实施方案中，存储器单元可以以预定的顺序编程，其允许在具有最低有效位（LSB）的编程页面之前首先编程具有最高有效位（MSB）和中央有效位（CSB）的页面，。该序列允许首先对相邻小区（例如，与目标小区相邻的小区）进行编程，以便减少要在后续阶段中编程的目标小区上的浮动栅极耦合干扰和阈值电压漂移。为了适应编程序列（例如，在设备级），可以添加附加的缓冲存储器。

14. 发明授权

US08638613B1 Flash memory 有权
标题翻译：闪存
公开(公告)号：US08638613B1
公开(公告)日：2014-01-28
申请号：US13538827
申请日：2012-06-29
申请人： Zining Wu , Xueshi Yang
发明人： Zining Wu , Xueshi Yang
IPC分类号： G11C16/00
CPC分类号： G11C16/12 , G11C7/04 , G11C16/10 , G11C16/26 , G11C16/30 , G11C16/34 , G11C16/3404 , G11C16/349
摘要： This disclosure describes techniques for using environmental variables to improve calibration of flash memory by adapting to changing threshold-voltage distributions. These techniques effectively increase the speed and/or accuracy at which flash memory can be written or read.
摘要翻译：本公开描述了通过适应变化的阈值电压分布来使用环境变量来改进闪速存储器校准的技术。这些技术有效地提高了可以写入或读取闪存的速度和/或精度。

15. 发明授权

US08347187B2 Adaptive systems and methods for storing and retrieving data to and from memory cells 有权
公开(公告)号：US08347187B2
公开(公告)日：2013-01-01
申请号：US13459013
申请日：2012-04-27
申请人： Xueshi Yang , Zining Wu
发明人： Xueshi Yang , Zining Wu
IPC分类号： H03M13/00
CPC分类号： G06F11/1048
摘要： Adaptive systems include a memory device including a plurality of memory cells, a data quality monitoring block, and an adaptive data encoding block, the data quality monitoring block and the adaptive data encoding block both being operatively coupled to the memory device. The data quality monitoring block is configured to determine a quality value of a group of one or more memory cells included in the memory device, the determined quality value being indicative of a quality of the group of one or more memory cells. The adaptive data encoding block is configured to select a coding scheme from a plurality of coding schemes to encode data to be written to the group of one or more memory cells in the memory device, the selection of the coding scheme being based at least in part on the determined quality value of the group of one or more memory cells.

16. 发明授权

US08339874B2 Sequence detection for flash memory with inter-cell interference 有权
标题翻译：具有小区间干扰的闪存的序列检测
公开(公告)号：US08339874B2
公开(公告)日：2012-12-25
申请号：US13335037
申请日：2011-12-22
申请人： Xueshi Yang , Zining Wu
发明人： Xueshi Yang , Zining Wu
IPC分类号： G11C7/22
CPC分类号： G11C16/04 , G11C7/02 , G11C7/14 , G11C16/06 , G11C16/26 , G11C16/3418 , G11C16/3422
摘要： A memory integrated circuit (IC) includes a read module and a sequence detector module. The read module reads S memory cells (cells) located along one of a bit line and a word line and generates S read signals, where S is an integer greater than 1. The sequence detector module detects a data sequence based on the S read signals and reference signals. The data sequence includes data stored in the S cells. Each of the reference signals includes an interference-free signal associated with one of the S cells and an interference signal associated with another of the S cells that is adjacent to the one of the S cells.
摘要翻译：存储器集成电路（IC）包括读取模块和序列检测器模块。读取模块读取沿着位线和字线中的一个位置的S个存储单元（单元），并产生S个读取信号，其中S是大于1的整数。序列检测器模块基于S个读取信号来检测数据序列和参考信号。数据序列包括存储在S单元中的数据。每个参考信号包括与S个小区中的一个相关联的无干扰信号和与S个小区之一相邻的S个小区中的另一个的干扰信号。

17. 发明授权

US08189381B1 System and method for reading flash memory cells 有权
标题翻译：用于读取闪存单元的系统和方法
公开(公告)号：US08189381B1
公开(公告)日：2012-05-29
申请号：US12194133
申请日：2008-08-19
申请人： Xueshi Yang , Zining Wu
发明人： Xueshi Yang , Zining Wu
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/3436
摘要： A memory system includes an array of X memory cells that each includes Y storage regions. The system also includes a read module that receives a first read signal that includes a first read signal data component and a first read signal interference component from a first one of the Y storage regions. The read module also receives a second read signal from a second one of the Y storage regions. The first interference component includes interference from the second one of the Y storage regions. The system also includes a data detection module that recovers the first read signal data component from the first read signal based on the second read signal and one or more of M noiseless signal estimates. M and X are integers greater than or equal to one, and Y is an integer greater than or equal to two.
摘要翻译：存储器系统包括每个包括Y个存储区域的X个存储器单元的阵列。该系统还包括读取模块，其从第一个Y存储区域接收包括第一读取信号数据分量和第一读取信号干扰分量的第一读取信号。读取模块还从第二个Y存储区域接收第二读取信号。第一干扰分量包括来自Y个存储区域中的第二个的干扰。该系统还包括数据检测模块，其基于第二读取信号和M个无噪声信号估计中的一个或多个，从第一读取信号中恢复第一读取信号数据分量。 M和X是大于或等于1的整数，Y是大于或等于2的整数。

18. 发明授权

US08164846B1 Hybrid defect detection for recording channels 有权
标题翻译：记录通道的混合缺陷检测
公开(公告)号：US08164846B1
公开(公告)日：2012-04-24
申请号：US12336308
申请日：2008-12-16
申请人： Xueshi Yang , Yu-Yao Chang , Michael Madden , Zining Wu
发明人： Xueshi Yang , Yu-Yao Chang , Michael Madden , Zining Wu
IPC分类号： G11B5/02 , G11B27/36
CPC分类号： G11B20/1816 , G11B2220/2516
摘要： Methods, systems and computer program products for performing hybrid defect detection are disclosed. A hybrid defect detection mechanism may be used to detect various classes of defects (e.g., long and shallow defects, and short and deep defects) while reducing the probability of a miss or false alarm. In some implementations, the hybrid defect detection mechanism may utilize a defect detector that includes one or more defect sub-detectors. Each defect sub-detector may be associated with an individual threshold and sliding window length to enhance the hybrid defect detection process that maximizes the detection of a specific type or class of defects.
摘要翻译：公开了用于执行混合缺陷检测的方法，系统和计算机程序产品。可以使用混合缺陷检测机构来检测各种类型的缺陷（例如，长而浅的缺陷以及短而深的缺陷），同时降低错误或虚假警报的可能性。在一些实施方案中，混合缺陷检测机构可以利用包括一个或多个缺陷子检测器的缺陷检测器。每个缺陷子检测器可以与单个阈值和滑动窗口长度相关联，以增强最大化特定类型或类别的缺陷的检测的混合缺陷检测过程。

19. 发明授权

US08077520B1 Determining threshold voltage distribution in flash memory 有权
标题翻译：确定闪存中的阈值电压分布
公开(公告)号：US08077520B1
公开(公告)日：2011-12-13
申请号：US12552925
申请日：2009-09-02
申请人： Xueshi Yang , Zining Wu , Gregory Burd
发明人： Xueshi Yang , Zining Wu , Gregory Burd
IPC分类号： G11C11/34
CPC分类号： G11C16/26 , G11C16/06 , G11C16/3404
摘要： Methods, apparatuses, and systems for comparing threshold voltages of a plurality of flash memory cells to a plurality of reference voltages. A number of flash memory cells having threshold voltages that fall within each bin of a plurality of bins is determined. The plurality of bins each represent a plurality of threshold voltage ranges. A threshold voltage distribution of the plurality of flash memory cells is calculated based at least in part on the number of flash memory cells that fall into each of the bins.
摘要翻译：用于将多个快闪存储器单元的阈值电压与多个参考电压进行比较的方法，装置和系统。确定具有落在多个箱体的每个箱体内的阈值电压的多个闪存单元。多个箱体各自表示多个阈值电压范围。至少部分地基于落入每个仓的闪存单元的数量来计算多个闪存单元的阈值电压分布。

20. 发明授权

US07974366B2 Low-latency baseline-wander compensation systems and methods 有权
标题翻译：低延迟基线漂移补偿系统和方法
公开(公告)号：US07974366B2
公开(公告)日：2011-07-05
申请号：US11520531
申请日：2006-09-12
申请人： Xueshi Yang , Zining Wu
发明人： Xueshi Yang , Zining Wu
IPC分类号： H04L25/06
CPC分类号： G11B20/10296 , G11B20/10203 , H03M13/41
摘要： Disclosed herein are systems and methods for detecting a signal to provide a detected data sequence, comprising providing a plurality of candidate data sequences, computing baseline wander estimates associated with respective ones of the candidate data sequences, comparing a signal to each of the respective ones of the candidate data sequences, wherein the comparisons are compensated by corresponding ones of the baseline wander estimates, and choosing, based on the comparisons, one of the plurality of candidate data sequences to be the detected data sequence.
摘要翻译：本文公开了用于检测信号以提供检测到的数据序列的系统和方法，包括提供多个候选数据序列，计算与候选数据序列中的相应数据序列相关联的基线漂移估计，将信号与候选数据序列，其中比较由对应的基线漂移估计补偿，并且基于比较，选择多个候选数据序列中的一个作为检测数据序列。

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