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11. 发明授权

US08946082B2 Methods for forming semiconductor devices 有权
标题翻译：半导体器件形成方法
公开(公告)号：US08946082B2
公开(公告)日：2015-02-03
申请号：US13235194
申请日：2011-09-16
申请人： Errol T. Ryan
发明人： Errol T. Ryan
IPC分类号： H01L21/44 , H01L21/768
CPC分类号： H01L21/76843 , H01L21/76856 , H01L21/76865
摘要： Embodiments of methods for forming a semiconductor device are provided. The method includes forming a metal layer overlying a dielectric material. A thickness of the metal layer is reduced including oxidizing an exposed outer portion of the metal layer to form a metal oxide portion overlying a remaining portion of the metal layer and removing the metal oxide portion.
摘要翻译：提供了形成半导体器件的方法的实施例。该方法包括形成覆盖电介质材料的金属层。减少金属层的厚度，包括氧化金属层的暴露的外部部分，以形成覆盖金属层的剩余部分并去除金属氧化物部分的金属氧化物部分。

12. 发明申请

US20130299994A1 INTEGRATED CIRCUITS AND PROCESSES FOR FORMING INTEGRATED CIRCUITS HAVING AN EMBEDDED ELECTRICAL INTERCONNECT WITHIN A SUBSTRATE 有权
标题翻译：用于形成在基板中嵌入电气互连的集成电路的集成电路和处理
公开(公告)号：US20130299994A1
公开(公告)日：2013-11-14
申请号：US13466895
申请日：2012-05-08
申请人： Chanro Park , Errol T. Ryan
发明人： Chanro Park , Errol T. Ryan
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76883 , H01L21/76832 , H01L21/76834
摘要： Integrated circuits and processes for forming integrated circuits are provided. An exemplary process for forming an integrated circuit includes providing a substrate including an oxide layer and a protecting layer disposed over the oxide layer. A recess is etched through the protecting layer and at least partially into the oxide layer. A barrier material is deposited in the recess to form a barrier layer over the oxide layer and protecting layer in the recess. Electrically-conductive material is deposited over the barrier layer in the recess to form the embedded electrical interconnect. The embedded electrical interconnect and barrier layer are recessed to an interconnect recess depth and a barrier recess depth, respectively, within the substrate. At least a portion of the protecting layer remains over the oxide layer after recessing the barrier layer and is removed after recessing the barrier layer.
摘要翻译：提供了用于形成集成电路的集成电路和工艺。用于形成集成电路的示例性方法包括提供包括氧化物层和设置在氧化物层上的保护层的衬底。通过保护层蚀刻凹陷，并且至少部分地蚀刻到氧化物层中。阻挡材料沉积在凹部中以在氧化物层和凹部中的保护层之上形成阻挡层。导电材料沉积在凹槽中的势垒层上以形成嵌入的电互连。嵌入的电互连和阻挡层分别凹陷到衬底内的互连凹槽深度和阻挡凹槽深度。在使阻挡层凹陷之后，保护层的至少一部分保留在氧化物层上方，并且在凹陷阻挡层之后被去除。

13. 发明授权

US08367562B2 Method for uniform nanoscale film deposition 有权
标题翻译：均匀纳米级膜沉积的方法
公开(公告)号：US08367562B2
公开(公告)日：2013-02-05
申请号：US12404890
申请日：2009-03-16
申请人： Errol T. Ryan
发明人： Errol T. Ryan
IPC分类号： H01L21/469
CPC分类号： H01L21/76834 , C23C16/345 , C23C16/45565 , C23C16/45587 , C23C16/4583 , C23C16/505 , H01L21/0217 , H01L21/02271 , H01L21/3185
摘要： Ultrathin layers are deposited by chemical vapor deposition (CVD) with reduced discontinuities, such as pinholes. Embodiments include depositing a material on a wafer by CVD while rotating the CVD showerhead and/or the wafer mounting surface, e.g., at least 45°. Embodiments include rotating the showerhead and/or mounting surface continuously through the deposition of the material. Embodiments also include forming subfilms of the material and rotating the showerhead and/or mounting surface after the deposition of each subfilm. The rotation of the showerhead and/or mounting surface averages out the non-uniformities introduced by the CVD showerhead, thereby eliminating discontinuities and improving within wafer and wafer-to-wafer uniformity.
摘要翻译：通过具有减小的不连续性（例如针孔）的化学气相沉积（CVD）沉积超薄层。实施例包括在旋转CVD喷头和/或晶片安装表面的情况下通过CVD在晶片上沉积材料，例如至少45°。实施例包括通过材料的沉积来连续旋转喷头和/或安装表面。实施例还包括在沉积每个子膜之后形成材料的子膜并旋转喷头和/或安装表面。喷头和/或安装面的旋转平均化了由CVD喷头引入的不均匀性，从而消除了晶片间的不连续性和提高晶片与晶片的均匀性。

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