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11. 发明授权

US09547355B2 Voltage regulator control for improved computing power efficiency 有权
标题翻译：电压调节器控制，提高计算能力效率
公开(公告)号：US09547355B2
公开(公告)日：2017-01-17
申请号：US14461988
申请日：2014-08-18
申请人： Wisconsin Alumni Research Foundation
发明人： Nam Sung Kim
IPC分类号： G06F1/32
CPC分类号： G06F1/3206 , G06F1/26 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172 , Y02D50/20
摘要： A controller for voltage regulators providing power to computer processors may control the number of active phases of each voltage regulator according to a determined electrical current demand from the processor. By relying on electrical current demand rather than a P-state, the latter generally indicating a power conservation status, improved regulator efficiencies may be had, in particular responding to situations where low current demand occurs under heavy processor demand because of C-state variations.
摘要翻译：用于向计算机处理器提供电力的稳压器的控制器可以根据来自处理器的确定的电流需求来控制每个电压调节器的有源相位的数量。通过依赖于电流需求而不是P-状态，后者通常表示节电状态，可能会改善调节器效率，特别是响应于由于C态变化而在重处理器需求下发生低电流需求的情况。

12. 发明授权

US09501227B2 Memory controller for heterogeneous computer 有权
标题翻译：内存控制器用于异构计算机
公开(公告)号：US09501227B2
公开(公告)日：2016-11-22
申请号：US14465126
申请日：2014-08-21
申请人： Wisconsin Alumni Research Foundation
发明人： Hao Wang , Nam Sung Kim
IPC分类号： G06F12/12 , G06F3/06
CPC分类号： G06F3/0611 , G06F3/0659 , G06F3/0683 , G06F3/0685 , G06F9/50 , G06F13/1668
摘要： A memory controller for heterogeneous computer processors dynamically adjusts access priorities by the different processors to maximize performance in the execution of a single parallel application program on both processor architectures. In one embodiment, the memory controller predicts sequential memory accesses by the processor having higher memory latency or fewer access requests to lockout the other processor during those sequences for improved implementation of the intended prioritization.
摘要翻译：用于异构计算机处理器的存储器控制器动态地调整不同处理器的访问优先级，以最大化在两个处理器架构上执行单个并行应用程序的性能。在一个实施例中，存储器控制器预测具有较高存储器等待时间的处理器的顺序存储器存取或较少的访问请求，以在那些序列期间锁定另一个处理器，以改进预期优先级的实现。

13. 发明申请

US20140337853A1 Resource And Core Scaling For Improving Performance Of Power-Constrained Multi-Core Processors 有权
标题翻译：用于提高功率约束多核处理器性能的资源和核心缩放
公开(公告)号：US20140337853A1
公开(公告)日：2014-11-13
申请号：US13889577
申请日：2013-05-08
申请人： WISCONSIN ALUMNI RESEARCH FOUNDATION
发明人： Nam Sung Kim
IPC分类号： G06F9/50
CPC分类号： G06F9/5094 , Y02D10/22
摘要： A multi-core processor provides circuitry for jointly scaling the number of operating cores and the amount of resources per core in order to maximize processing performance in a power-constrained environment. Such scaling is advantageously provided without the need for scaling voltage and frequency. Selection of the number of operating cores and the amount of resources per core is made by examining the degree of instruction and thread level parallelism available for a given application. Accordingly, performance counters (and other characteristics) implemented in by a processor may be sampled on-line (in real time) and/or performance counters for a given application may be profiled and characterized off-line. As a result, improved processing performance may be achieved despite decreases in core operating voltages and increases in technology process variability over time.
摘要翻译：多核处理器提供用于联合扩展操作核心数量和每个核心资源量的电路，以便在功率受限环境中最大化处理性能。有利地提供这种缩放，而不需要缩放电压和频率。通过检查给定应用程序可用的指令程度和线程级并行度，可以选择每个内核的操作核心数量和资源量。因此，处理器实现的性能计数器（和其他特性）可以在线（实时）进行采样，并且/或者用于给定应用的性能计数器可以被离线地表征和表征。因此，虽然核心工作电压降低，但随着时间的推移技术工艺变化性的增加，可以实现改进的处理性能。

14. 发明授权

US10108220B2 Computer architecture having selectable, parallel and serial communication channels between processors and memory 有权
公开(公告)号：US10108220B2
公开(公告)日：2018-10-23
申请号：US14267190
申请日：2014-05-01
申请人： Wisconsin Alumni Research Foundation
发明人： Hao Wang , Nam Sung Kim
IPC分类号： G06F1/10 , G06F13/40 , G06F13/42 , G06F13/16 , G06F3/06
摘要： A computer architecture provides both a parallel memory bus and serial memory bus between a processor system and memory. Latency-tolerant memory access requests are steered to the serial memory bus which operates to increase the available memory bus bandwidth on the parallel memory. The invention also provides integrated circuit computer memory suitable for this application.

15. 发明授权

US09639328B2 Multiplication circuit providing dynamic truncation 有权
公开(公告)号：US09639328B2
公开(公告)日：2017-05-02
申请号：US14453172
申请日：2014-08-06
申请人： Wisconsin Alumni Research Foundation
发明人： Srinivasan Narayanamoorthy , Nam Sung Kim
IPC分类号： G06F7/38 , G06F7/523 , G06F1/32 , G06F7/499
CPC分类号： G06F7/523 , G06F1/32 , G06F7/49936
摘要： A fixed-point multiplier providing reduced energy usage dynamically truncates received operands according to the location of computationally important bits in the operands and provides the truncated operands to a reduced width multiplier offering reduced energy usage. Information about the location of the dynamic truncation is used to properly shift the result of the multiplier to provide an approximation of full multiplication of the operands.

16. 发明授权

US09606842B2 Resource and core scaling for improving performance of power-constrained multi-core processors 有权
公开(公告)号：US09606842B2
公开(公告)日：2017-03-28
申请号：US13889577
申请日：2013-05-08
申请人： Wisconsin Alumni Research Foundation
发明人： Nam Sung Kim
IPC分类号： G06F9/46 , G06F9/50
CPC分类号： G06F9/5094 , Y02D10/22
摘要： A multi-core processor provides circuitry for jointly scaling the number of operating cores and the amount of resources per core in order to maximize processing performance in a power-constrained environment. Such scaling is advantageously provided without the need for scaling voltage and frequency. Selection of the number of operating cores and the amount of resources per core is made by examining the degree of instruction and thread level parallelism available for a given application. Accordingly, performance counters (and other characteristics) implemented in by a processor may be sampled on-line (in real time) and/or performance counters for a given application may be profiled and characterized off-line. As a result, improved processing performance may be achieved despite decreases in core operating voltages and increases in technology process variability over time.

17. 发明授权

US09519459B2 High efficiency computer floating point multiplier unit 有权
标题翻译：高效电脑浮点乘数单元
公开(公告)号：US09519459B2
公开(公告)日：2016-12-13
申请号：US14310868
申请日：2014-06-20
申请人： Wisconsin Alumni Research Foundation
发明人： Nam Sung Kim , Syed Gilani , Michael Schulte
IPC分类号： G06F7/487
CPC分类号： G06F7/4876
摘要： A high-power-efficiency multiplier combines a standard floating-point multiplier with a power-of-two multiplier that performs multiplications by shifting operations without the need for floating-point multiplication circuitry. By selectively steering some operands to this power-of-two multiplier, substantial power savings may be realized. In one embodiment, multiplicands may be modified to work with the power-of-two multiplier introducing low errors that may be accommodated in pixel calculations.
摘要翻译：大功率效率乘法器将标准浮点乘法器与功率二乘法器相结合，通过移位运算执行乘法，而不需要浮点乘法电路。通过选择性地将一些操作数转向这个二功率乘法器，可以实现大量的功率节省。在一个实施例中，被乘数可以被修改为与二乘法器乘法器一起工作，引入可能适应于像素计算的低误差。

18. 发明授权

US09323498B2 Multiplier circuit with dynamic energy consumption adjustment 有权
标题翻译：具有动态能量消耗调节的乘法电路
公开(公告)号：US09323498B2
公开(公告)日：2016-04-26
申请号：US13800709
申请日：2013-03-13
申请人： WISCONSIN ALUMNI RESEARCH FOUNDATION
发明人： Nam Sung Kim
IPC分类号： G06F7/52 , G06F7/499 , G06F7/53
CPC分类号： G06F7/49942 , G06F7/53
摘要： A fixed point multiplier that can be used in mobile computer systems operating under limited power constraints provides a trade-off between computational accuracy and energy consumption that may be changed dynamically for energy conservation purposes. In one embodiment, the multiplier pre-stores multiplication shift coefficients to eliminate leading-one circuitry normally used in shift and accumulate multipliers.
摘要翻译：可用于在有限功率约束条件下运行的移动计算机系统中的固定点乘数提供了计算精度和能量消耗之间的折衷，可以动态地改变节能目的。在一个实施例中，乘法器预存储乘法偏移系数以消除通常用于移位和累积乘法器的前导电路。

19. 发明申请

US20160054932A1 Memory Controller for Heterogeneous Computer 有权
标题翻译：用于异构计算机的内存控制器
公开(公告)号：US20160054932A1
公开(公告)日：2016-02-25
申请号：US14465126
申请日：2014-08-21
申请人： Wisconsin Alumni Research Foundation
发明人： Hao Wang , Nam Sung Kim
IPC分类号： G06F3/06
CPC分类号： G06F3/0611 , G06F3/0659 , G06F3/0683 , G06F3/0685 , G06F9/50 , G06F13/1668
摘要： A memory controller for heterogeneous computer processors dynamically adjusts access priorities by the different processors to maximize performance in the execution of a single parallel application program on both processor architectures. In one embodiment, the memory controller predicts sequential memory accesses by the processor having higher memory latency or fewer access requests to lockout the other processor during those sequences for improved implementation of the intended prioritization.
摘要翻译：用于异构计算机处理器的存储器控制器动态地调整不同处理器的访问优先级，以最大化在两个处理器架构上执行单个并行应用程序的性能。在一个实施例中，存储器控制器预测具有较高存储器等待时间的处理器的顺序存储器存取或较少的访问请求，以在那些序列期间锁定另一个处理器，以改进预期优先级的实现。

20. 发明申请

US20160048188A1 Voltage Regulator Control for Improved Computing Power Efficiency 有权
标题翻译：电压调节器控制，提高计算能耗
公开(公告)号：US20160048188A1
公开(公告)日：2016-02-18
申请号：US14461988
申请日：2014-08-18
申请人： Wisconsin Alumni Research Foundation
发明人： Nam Sung Kim
IPC分类号： G06F1/32
CPC分类号： G06F1/3206 , G06F1/26 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172 , Y02D50/20
摘要： A controller for voltage regulators providing power to computer processors may control the number of active phases of each voltage regulator according to a determined electrical current demand from the processor. By relying on electrical current demand rather than a P-state, the latter generally indicating a power conservation status, improved regulator efficiencies may be had, in particular responding to situations where low current demand occurs under heavy processor demand because of C-state variations.
摘要翻译：用于向计算机处理器提供电力的稳压器的控制器可以根据来自处理器的确定的电流需求来控制每个电压调节器的有源相位的数量。通过依赖于电流需求而不是P-状态，后者通常表示节电状态，可能会改善调节器效率，特别是响应于由于C态变化而在重处理器需求下发生低电流需求的情况。

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