专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20050001171A1 SILICON-ON-INSULATOR LATCH-UP PULSE-RADIATION DETECTOR 有权
标题翻译：绝缘子绝缘子放电脉冲辐射检测器
公开(公告)号：US20050001171A1
公开(公告)日：2005-01-06
申请号：US10604204
申请日：2003-07-01
申请人： Peter Cottrell , Robert Dennard , Edward Nowak , Norman Rohrer
发明人： Peter Cottrell , Robert Dennard , Edward Nowak , Norman Rohrer
IPC分类号： H01L27/12 , G01T1/24 , H01L31/111
CPC分类号： H01L31/1113
摘要： A radiation detector formed using silicon-on-insulator technology. The radiation detector includes a silicon layer formed on an insulating substrate, wherein the silicon layer includes a PNPN structure, and a gate layer formed over the PNPN structure, wherein the gate layer includes a PN gate. Latch-up occurs in the radiation detector only in response to incident radiation.
摘要翻译：使用绝缘体上硅技术形成的放射线检测器。放射线检测器包括形成在绝缘基板上的硅层，其中硅层包括PNPN结构，以及形成在PNPN结构上的栅极层，其中栅极层包括PN栅极。仅在响应入射辐射的情况下，在辐射探测器中发生锁定。

12. 发明申请

US20050037582A1 DEVICE THRESHOLD CONTROL OF FRONT-GATE SILICON-ON-INSULATOR MOSFET USING A SELF-ALIGNED BACK-GATE 失效
标题翻译：使用自对准后门的前栅绝缘体MOSFET的器件阈值控制
公开(公告)号：US20050037582A1
公开(公告)日：2005-02-17
申请号：US10639942
申请日：2003-08-13
申请人： Robert Dennard , Wilfried Haensch , Hussein Hanafi
发明人： Robert Dennard , Wilfried Haensch , Hussein Hanafi
IPC分类号： H01L21/336 , H01L21/762 , H01L29/786 , H01L21/00
CPC分类号： H01L29/78696 , H01L21/76256 , H01L21/76275 , H01L29/66772 , H01L29/78648 , H01L29/78654
摘要： The present invention provides SOI CMOS technology whereby a polysilicon back-gate is used to control the threshold voltage of the front-gate device, and the nMOS and pMOS back-gates are switched independently of each other and the front gates. Specifically, the present invention provides a method of fabricating a back-gated fully depleted CMOS device in which the device's back-gate is self-aligned to the device's front-gate as well as the source/drain extension. Such a structure minimizes the capacitance, while enhancing the device and circuit performance. The back-gated fully depleted CMOS device of the present invention is fabricated using existing SIMOX (separation by ion implantation of oxygen) or bonded SOI wafers, wafer bonding and thinning, polySi etching, low-pressure chemical vapor deposition and chemical-mechanical polishing.
摘要翻译：本发明提供SOI CMOS技术，由此使用多晶硅背栅极来控制前栅极器件的阈值电压，并且nMOS和pMOS反向栅极彼此独立地切换和前栅极。具体地说，本发明提供了一种制造背栅绝缘的CMOS器件的方法，其中器件的背栅与器件的前栅极以及源极/漏极延伸部分自对准。这种结构使电容最小化，同时增强了器件和电路性能。使用现有的SIMOX（通过离子注入氧气进行分离）或接合的SOI晶片，晶片键合和变薄，多晶硅蚀刻，低压化学气相沉积和化学机械抛光来制造本发明的后栅极完全耗尽的CMOS器件。

13. 发明申请

US20050023664A1 High density chip carrier with integrated passive devices 有权
标题翻译：具有集成无源器件的高密度芯片载体
公开(公告)号：US20050023664A1
公开(公告)日：2005-02-03
申请号：US10930304
申请日：2004-08-31
申请人： Michael Chudzik , Robert Dennard , Rama Divakaruni , Bruce Kenneth Furman , Rajarao Jammy , Chandrasekhar Narayan , Sampath Purushothaman , Joseph Shepard , Anna Wanda Topol
发明人： Michael Chudzik , Robert Dennard , Rama Divakaruni , Bruce Kenneth Furman , Rajarao Jammy , Chandrasekhar Narayan , Sampath Purushothaman , Joseph Shepard , Anna Wanda Topol
IPC分类号： H01L23/12 , H01L23/50 , H01L25/04 , H01L25/18 , H01L29/40 , H05K1/16 , H05K3/46 , H01L21/44 , H01L23/02 , H01L23/52
CPC分类号： H05K1/162 , H01L23/147 , H01L23/481 , H01L23/49827 , H01L23/50 , H01L2224/16225 , H01L2924/01019 , H01L2924/01055 , H01L2924/01077 , H01L2924/01078 , H01L2924/15311 , H01L2924/157 , H01L2924/30105 , H05K1/167 , H05K3/4602 , H05K2201/09809
摘要： A carrier for a semiconductor component is provided having passive components integrated in its substrate. The passive components include decoupling components, such as capacitors and resistors. A set of connections is integrated to provide a close electrical proximity to the supported components.
摘要翻译：提供了一种用于半导体部件的载体，其具有集成在其基板中的无源部件。无源组件包括去耦组件，例如电容器和电阻器。一组连接被集成以提供与受支持的部件的紧密的电气接近。

14. 发明申请

US20060146638A1 MEMORY CELL HAVING IMPROVED READ STABILITY 有权
标题翻译：具有改进的读取稳定性的存储单元
公开(公告)号：US20060146638A1
公开(公告)日：2006-07-06
申请号：US11069018
申请日：2005-02-28
申请人： Leland Chang , Robert Dennard , Robert Kevin Montoye
发明人： Leland Chang , Robert Dennard , Robert Kevin Montoye
IPC分类号： G11C8/00
CPC分类号： G11C11/413 , H01L27/11 , H01L27/1104
摘要： A memory cell for use in a memory array includes a storage element for storing a logical state of the memory cell, a write circuit and a read circuit. The write circuit is operative to selectively connect a first node of the storage element to at least a first write bit line in the memory array in response to a write signal for selectively writing the logical state of the memory cell. The read circuit includes a substantially high impedance input node connected to the storage element and an output node connectable to a read bit line of the memory array. The read circuit is configured to generate an output signal at the output node which is representative of the logical state of the storage element in response to a read signal applied to the read circuit. The memory cell is configured such that the write circuit is disabled during a read operation of the memory cell so as to substantially isolate the storage element from the first write bit line during the read operation. A strength of at least one transistor device in the storage element is separately optimized relative to a strength of at least one transistor device in the write circuit and/or the read circuit.
摘要翻译：用于存储器阵列的存储单元包括用于存储存储单元的逻辑状态的存储元件，写入电路和读取电路。写入电路用于响应于用于选择性地写入存储器单元的逻辑状态的写入信号，有选择地将存储元件的第一节点连接到存储器阵列中的至少第一写入位线。读取电路包括连接到存储元件的基本上高阻抗的输入节点和可连接到存储器阵列的读取位线的输出节点。读取电路被配置为响应于施加到读取电路的读取信号而在输出节点处产生代表存储元件的逻辑状态的输出信号。存储单元被配置为使得在存储单元的读取操作期间禁止写入电路，以便在读取操作期间基本上将存储元件与第一写入位线隔离。存储元件中的至少一个晶体管器件的强度相对于写入电路和/或读取电路中的至少一个晶体管器件的强度分别优化。

15. 发明申请

US20050048703A1 Method to control device threshold of SOI MOSFET's 失效
标题翻译：控制SOI MOSFET器件阈值的方法
公开(公告)号：US20050048703A1
公开(公告)日：2005-03-03
申请号：US10965992
申请日：2004-10-15
申请人： Robert Dennard , Wilfried Haensch , Hussein Hanafi
发明人： Robert Dennard , Wilfried Haensch , Hussein Hanafi
IPC分类号： H01L21/336 , H01L29/45 , H01L29/786 , H01L21/00 , H01L21/30 , H01L21/84
CPC分类号： H01L29/66772 , H01L29/458 , H01L29/78621 , H01L29/78648
摘要： A method of forming a silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) device is provided in which an implanted back-gate is formed into a Si-containing layer of an SOI wafer. The implanted back-gate thus formed is capable of controlling the threshold voltage of a polysilicon-containing front-gate which is formed over a portion of the implanted back-gate region. The implanted back-gate functions as a dynamic threshold voltage control system in the SOI MOSFET device because it is suitable for use during circuit/system active periods and during circuit/system idle periods.
摘要翻译：提供了一种形成绝缘体上硅（SOI）金属氧化物半导体场效应晶体管（MOSFET）器件的方法，其中注入的背栅极形成为SOI晶片的含Si层。如此形成的注入后栅极能够控制在植入的背栅区域的一部分上形成的含多晶硅的前栅的阈值电压。在SOI MOSFET器件中，植入式背栅可用作动态阈值电压控制系统，因为它适用于电路/系统有效期间和电路/系统空闲期间。

16. 发明申请

US20050204319A1 Threshold voltage roll-off compensation using back-gated mosfet devices for system high-performance and low standby power 有权
标题翻译：使用后门控mosfet器件进行系统高性能和低待机功耗的阈值电压滚降补偿
公开(公告)号：US20050204319A1
公开(公告)日：2005-09-15
申请号：US10796805
申请日：2004-03-09
申请人： Hussein Hanafi , Robert Dennard , Wilfried Haensch
发明人： Hussein Hanafi , Robert Dennard , Wilfried Haensch
IPC分类号： G06F17/50
CPC分类号： H03K19/0013
摘要： A method for compensating the threshold voltage roll-off using transistors containing back-gates or body nodes is provided. The method includes designing a semiconductor system or chip having a plurality of transistors with a channel length of Lnom. For the present invention, it is assumed that the channel length of these transistors at the completion of chip manufacturing is Lmax. This enables one to set the off-current to the maximum value of I-offmax which is done by setting the threshold voltage value to Vtmin. The Vtmin for these transistors is obtained during processing by using the proper implant dose. After manufacturing, the transistors are then tested to determine the off-current thereof. Some transistors within the system or chip will have an off-current value that meets a current specification. For those transistor devices, no further compensation is required. For other transistors within the system or chip, the off-current is not within the predetermined specification. For those transistors, threshold voltage roll-off has occurred since they are transistors that have a channel length that is less than nominal. For such short channel transistors, the threshold voltage is low, even lower than Vtmin, and the off-current is high, even higher than I-offmax. Compensation of the short channel transistors is achieved in the present invention by biasing the back-gate or body node to give increased threshold voltage about equal to Vtmin and hence an off-current that meets the predetermined specification, which is about equal to I-offmax.
摘要翻译：提供了使用包含背栅或体节点的晶体管补偿阈值电压滚降的方法。该方法包括设计具有通道长度为L nom的多个晶体管的半导体系统或芯片。对于本发明，假设在芯片制造完成时这些晶体管的沟道长度为L max max。这使得能够将截止电流设置为通过将阈值电压值设置为Vt分钟来完成的I-OFF 的最大值。通过使用适当的植入剂量，在处理期间获得这些晶体管的Vt 。在制造之后，然后测试晶体管以确定其截止电流。系统或芯片内的一些晶体管将具有满足当前规范的截止值。对于那些晶体管器件，不需要进一步的补偿。对于系统或芯片内的其他晶体管，截止电流不在预定的规范内。对于那些晶体管，已经发生阈值电压滚降，因为它们是具有小于额定值的沟道长度的晶体管。对于这种短沟道晶体管，阈值电压低，甚至低于Vt分钟<！ - SIPO - >，并且截止电流高，甚至高于I-off最大值。在本发明中通过偏置背栅极或体节点以提供大约等于Vt分钟的阈值电压，从而达到满足预定规格的截止电流来实现短沟道晶体管的补偿，其大约等于I-off最大。

17. 发明申请

US20070138533A1 Substrate solution for back gate controlled SRAM with coexisting logic devices 有权
标题翻译：用于具有共存逻辑器件的背栅控制SRAM的衬底解决方案
公开(公告)号：US20070138533A1
公开(公告)日：2007-06-21
申请号：US11311462
申请日：2005-12-19
申请人： Robert Dennard , Wilfried Haensch , Arvind Kumar , Robert Miller
发明人： Robert Dennard , Wilfried Haensch , Arvind Kumar , Robert Miller
IPC分类号： H01L29/76
CPC分类号： H01L27/1108
摘要： A semiconductor structure that includes at least one logic device region and at least one static random access memory (SRAM) device region wherein each device region includes a double gated field effect transistor (FET) wherein the back gate of each of the FET devices is doped to a specific level so as to improve the performance of the FET devices within the different device regions is provided. In particular, the back gate within the SRAM device region is more heavily doped than the back gate within the logic device region. In order to control short channel effects, the FET device within the logic device region includes a doped channel, while the FET device within the SRAM device region does not. A none uniform lateral doping profile with a low net doping beneath the source/drain regions and a high net doping underneath the channel would provide additional SCE control for the logic device
摘要翻译：一种半导体结构，其包括至少一个逻辑器件区域和至少一个静态随机存取存储器（SRAM）器件区域，其中每个器件区域包括双门控场效应晶体管（FET），其中每个FET器件的背栅极掺杂提供了特定的水平，以提高不同器件区域内的FET器件的性能。特别地，SRAM器件区域内的背栅极比逻辑器件区域内的后栅极重掺杂。为了控制短沟道效应，逻辑器件区域内的FET器件包括掺杂沟道，而SRAM器件区域内的FET器件不是。在源极/漏极区域之下具有低净掺杂的无均匀横向掺杂分布以及在沟道下方的高净掺杂将为逻辑器件提供附加的SCE控制

18. 发明申请

US20060030133A1 Relaxed, low-defect SGOI for strained Si CMOS applications 有权
标题翻译：用于应变Si CMOS应用的轻松，低缺陷SGOI
公开(公告)号：US20060030133A1
公开(公告)日：2006-02-09
申请号：US11208359
申请日：2005-08-19
申请人： Paul Agnello , Stephen Bedell , Robert Dennard , Anthony Domenicucci , Keith Fogel , Devendra Sadana
发明人： Paul Agnello , Stephen Bedell , Robert Dennard , Anthony Domenicucci , Keith Fogel , Devendra Sadana
IPC分类号： H01L21/20 , H01L33/00 , H01L21/36
CPC分类号： H01L21/324 , C30B25/02 , C30B29/52 , H01L21/02378 , H01L21/02381 , H01L21/02532 , H01L21/02664 , H01L21/7624 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/66893 , H01L29/78603
摘要： Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.
摘要翻译：提供形成基本上松弛和低缺陷的SGOI基底材料的热混合方法。所述方法包括图形化步骤，其用于形成至少包含形成在Ge抗蚀扩散阻挡层顶上的SiGe岛的结构。将SiGe层图案化成岛以这样的方式改变作用在每个岛边缘处的局部力，使得松弛力大于抵抗放松的力。在图案化层的边缘处没有恢复力允许最终的SiGe膜比如果膜是连续的那样进一步松弛。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式