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11. 发明授权

US06418529B1 Apparatus and method for performing intra-add operation 失效
标题翻译：用于执行增加操作的装置和方法
公开(公告)号：US06418529B1
公开(公告)日：2002-07-09
申请号：US09053401
申请日：1998-03-31
申请人： Patrice Roussel
发明人： Patrice Roussel
IPC分类号： G06F9302
CPC分类号： G06F9/30036 , G06F9/3001
摘要： Method and apparatus for including in a processor, instructions for performing intra-add operations on packed data. In one embodiment, an execution unit is coupled to a storage area. The storeage area has stored therein a first packed data operand and a second packed data operand. The execution unit performs operations on data elements in the first packed data operand and the second packed data operand to generate a plurality of data elements in a packed data result in response to receiving a single instruction. At least two of the plurality of data elements in a packed data result store the result of an intra-add operation using the first packed data operand and the second packed data operand.
摘要翻译：在处理器中包括用于对打包数据执行加载操作的指令的方法和装置。在一个实施例中，执行单元耦合到存储区域。存储区域中存储有第一打包数据操作数和第二打包数据操作数。执行单元对第一打包数据操作数和第二压缩数据操作数中的数据元素执行操作，以响应于接收到单个指令而产生打包数据结果中的多个数据元素。打包数据结果中的多个数据元素中的至少两个数据结果使用第一打包数据操作数和第二打包数据操作数存储加入内操作的结果。

12. 发明授权

US06317824B1 Method and apparatus for performing integer operations in response to a result of a floating point operation 失效
标题翻译：响应于浮点运算的结果执行整数运算的方法和装置
公开(公告)号：US06317824B1
公开(公告)日：2001-11-13
申请号：US09049827
申请日：1998-03-27
申请人： Shreekant S. Thakkar , Wayne H. Scott , Patrice Roussel
发明人： Shreekant S. Thakkar , Wayne H. Scott , Patrice Roussel
IPC分类号： G06F1500
CPC分类号： G06F9/30018 , G06F9/30021 , G06F9/30036 , G06F9/30094 , G06F9/30109 , G06F9/30112 , G06F9/3013
摘要： A method and apparatus for performing a move mask operation. The present invention provides a method and apparatus for performing operations on packed data values of a first size and format and conversion of the results to data of a second size and format by eliminating redundant data. The present invention is useful, for example, when comparisons are performed on floating point data that is typically larger (e.g., 64 bits) than integer data (e.g., 32 bits) and integer operations are preformed based on the result. Because many processors branch based on integer data, the comparison results stored as floating point data must be transferred to an integer register prior to branching. The present invention takes advantage of redundancy of the floating point comparison results to transfer enough data to convey the comparison result to integer registers with a single instruction.
摘要翻译：一种用于执行移动掩模操作的方法和装置。本发明提供了一种用于对第一大小和格式的打包数据值执行操作的方法和装置，并且通过消除冗余数据将结果转换成第二大小和格式的数据。本发明例如在对通常比整数数据（例如，32位）更大（例如，64位））的浮点数据执行比较时是有用的，并且基于结果执行整数运算。由于许多处理器基于整数数据分支，所以作为浮点数据存储的比较结果必须在分支之前传输到整数寄存器。本发明利用浮点比较结果的冗余来传送足够的数据，以将比较结果传达给具有单个指令的整数寄存器。

13. 发明授权

US5995122A Method and apparatus for parallel conversion of color values from a single precision floating point format to an integer format 失效
标题翻译：将颜色值从单精度浮点格式并行转换为整数格式的方法和装置
公开(公告)号：US5995122A
公开(公告)日：1999-11-30
申请号：US71468
申请日：1998-04-30
申请人： Hsien-Cheng E. Hsieh , Thomas R. Huff , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
发明人： Hsien-Cheng E. Hsieh , Thomas R. Huff , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
IPC分类号： H03M7/24 , G06F13/00 , G06F15/80
CPC分类号： H03M7/24
摘要： A method and apparatus for parallel processing of graphics data are described. A number of color components are stored in a floating point format in at least one register of a set of 128-bit registers in a packed format. The color components in the floating point format are converted to numbers in an integer format. The numbers in the integer format are placed in at least one register of a set of 64-bit registers in the packed format. Color components are assembled for image pixels from the numbers in the integer format.
摘要翻译：描述用于并行处理图形数据的方法和装置。多个颜色分量以压缩格式在一组128位寄存器的至少一个寄存器中以浮点格式存储。浮点格式的颜色分量将以整数格式转换为数字。整数格式的数字以打包格式放置在一组64位寄存器的至少一个寄存器中。从整数格式的数字组装图像像素的颜色分量。

14. 发明授权

US07853778B2 Load/move and duplicate instructions for a processor 有权
标题翻译：加载/移动和重复处理器的指令
公开(公告)号：US07853778B2
公开(公告)日：2010-12-14
申请号：US10032144
申请日：2001-12-20
申请人： Patrice Roussel
发明人： Patrice Roussel
IPC分类号： G06F9/00 , G06F15/00 , G06F15/76 , G06F7/38 , G06F9/44
CPC分类号： G06F9/3001 , G06F9/30032 , G06F9/30036 , G06F9/30043
摘要： A method includes, in a processor, loading/moving a first portion of bits of a source into a first portion of a destination register and duplicate that first portion of bits in a subsequent portion of the destination register.
摘要翻译：一种方法包括在处理器中将源的位的第一部分加载/移动到目的地寄存器的第一部分中，并且复制目的地寄存器的后续部分中的位的第一部分。

15. 发明授权

US06694426B2 Method and apparatus for staggering execution of a single packed data instruction using the same circuit 有权
公开(公告)号：US06694426B2
公开(公告)日：2004-02-17
申请号：US10164774
申请日：2002-06-06
申请人： Patrice Roussel , Glenn J. Hinton , Shreekant S. Thakkar , Brent R. Boswell , Karol F. Menezes
发明人： Patrice Roussel , Glenn J. Hinton , Shreekant S. Thakkar , Brent R. Boswell , Karol F. Menezes
IPC分类号： G06F1500
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/3826 , G06F9/3828 , G06F9/3875 , G06F9/3885
摘要： A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.

16. 发明授权

US06502115B2 Conversion between packed floating point data and packed 32-bit integer data in different architectural registers 有权
标题翻译：在不同体系结构寄存器中的打包浮点数据和打包的32位整数数据之间进行转换
公开(公告)号：US06502115B2
公开(公告)日：2002-12-31
申请号：US09845610
申请日：2001-04-27
申请人： Mohammad A. F. Abdallah , Hsien-Cheng E. Hsieh , Thomas R. Huff , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
发明人： Mohammad A. F. Abdallah , Hsien-Cheng E. Hsieh , Thomas R. Huff , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
IPC分类号： G06F700
CPC分类号： H03M7/24
摘要： A method and instruction for converting a number between a floating point format and an integer format are described. Numbers are stored in the integer format in a register of a first set of architectural registers in a packed format. At least one of the numbers in the integer format is converted to at least one number in the floating point format. The numbers in the floating point format are placed in a register of a second set of architectural registers in a packed format.
摘要翻译：描述用于在浮点格式和整数格式之间转换数字的方法和指令。数字以整数格式存储在打包格式的第一组架构寄存器的寄存器中。整数格式中的至少一个数字将以浮点格式转换为至少一个数字。浮点格式的数字以打包格式放置在第二组结构寄存器的寄存器中。

17. 发明授权

US06480868B2 Conversion from packed floating point data to packed 8-bit integer data in different architectural registers 有权
标题翻译：从打包浮点数据转换为不同架构寄存器中的8位整数数据
公开(公告)号：US06480868B2
公开(公告)日：2002-11-12
申请号：US09844728
申请日：2001-04-27
申请人： Mohammad A.F. Abdallah , Hsien-Cheng E. Hsieh , Thomas R. Huff , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
发明人： Mohammad A.F. Abdallah , Hsien-Cheng E. Hsieh , Thomas R. Huff , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
IPC分类号： G06F7100
CPC分类号： G06F9/30014 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/3013
摘要： A method and instruction for converting a number from a floating point format to an integer format are described. Numbers are stored in the floating point format in a register of a first set of architectural registers in a packed format. At least one of the numbers in the floating point format is converted to at least one 8-bit number in the integer format. The 8-bit number in the integer format is placed in a register of a second set of architectural registers in the packed format.
摘要翻译：描述用于将数字从浮点格式转换为整数格式的方法和指令。数字以浮点格式存储在打包格式的第一组结构寄存器的寄存器中。浮点格式中的至少一个数字将以整数格式转换为至少一个8位数。整数格式的8位数字以打包格式放置在第二组架构寄存器的寄存器中。

18. 发明授权

US06425073B1 Method and apparatus for staggering execution of an instruction 有权
公开(公告)号：US06425073B1
公开(公告)日：2002-07-23
申请号：US09805280
申请日：2001-03-13
申请人： Patrice Roussel , Glenn J. Hinton , Shreekant S. Thakkar , Brent R. Boswell , Karol F. Menezes
发明人： Patrice Roussel , Glenn J. Hinton , Shreekant S. Thakkar , Brent R. Boswell , Karol F. Menezes
IPC分类号： G06F900
摘要： A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.

19. 发明授权

US06263426B1 Conversion from packed floating point data to packed 8-bit integer data in different architectural registers 失效
公开(公告)号：US06263426B1
公开(公告)日：2001-07-17
申请号：US09070900
申请日：1998-04-30
申请人： Mohammad A. F. Abdallah , Hsien-Cheng E. Hsieh , Thomas R. Huff , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
发明人： Mohammad A. F. Abdallah , Hsien-Cheng E. Hsieh , Thomas R. Huff , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
IPC分类号： G06F900
CPC分类号： G06F9/30014 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/3013
摘要： A method and instruction for converting a number from a floating point format to an integer format are described. Numbers are stored in the floating point format in a register of a first set of architectural registers in a packed format. At least one of the numbers in the floating point format is converted to at least one 8-bit number in the integer format. The 8-bit number in the integer format is placed in a register of a second set of architectural registers in the packed format.

20. 发明授权

US06230253B1 Executing partial-width packed data instructions 失效
标题翻译：执行部分宽度打包的数据指令
公开(公告)号：US06230253B1
公开(公告)日：2001-05-08
申请号：US09053127
申请日：1998-03-31
申请人： Patrice Roussel , Ticky Thakkar
发明人： Patrice Roussel , Ticky Thakkar
IPC分类号： G06F922
CPC分类号： G06F9/3875 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/3013 , G06F9/30134 , G06F9/30145 , G06F9/30167 , G06F9/3017 , G06F9/30181 , G06F9/30196 , G06F9/384 , G06F9/3885
摘要： A method and apparatus are provided for executing scalar packed data instructions. According to one aspect of the invention, a processor includes a plurality of registers, a register renaming unit coupled to the plurality of registers, a decoder coupled to the register renaming unit, and a partial-width execution unit coupled to the decoder. The register renaming unit provides an architectural register file to store packed data operands each of which include a plurality of data elements. The decoder is configured to decode a first and second set of instructions that each specify one or more registers in the architectural register file. Each of the instructions in the first set of instructions specify operations to be performed on all of the data elements stored in the one or more specified registers. In contrast, each of the instructions in the second set of instructions specify operations to be performed on only a subset of the data element stored in the one or more specified registers. The partial-width execution unit is configured to execute operations specified by either of the first or the second set of instructions.
摘要翻译：提供了一种用于执行标量打包数据指令的方法和装置。根据本发明的一个方面，处理器包括多个寄存器，耦合到多个寄存器的寄存器重命名单元，耦合到寄存器重命名单元的解码器以及耦合到解码器的部分宽度执行单元。寄存器重命名单元提供架构寄存器文件以存储打包数据操作数，每个数据操作数包括多个数据元素。解码器被配置为解码每个指定体系结构寄存器文件中的一个或多个寄存器的第一和第二组指令。第一组指令中的每个指令指定要对存储在一个或多个指定寄存器中的所有数据元素执行的操作。相反，第二组指令中的每个指令指定仅对存储在一个或多个指定寄存器中的数据元素的子集执行的操作。部分宽度执行单元被配置为执行由第一或第二组指令指定的操作。

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