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11. 发明申请

US20110097889A1 STI Shape Near Fin Bottom of Si Fin in Bulk FinFET 有权
标题翻译：在散装FinFET中的Si Fin附近的STI形状的STI形状
公开(公告)号：US20110097889A1
公开(公告)日：2011-04-28
申请号：US12843693
申请日：2010-07-26
申请人： Feng Yuan , Tsung-Lin Lee , Hung-Ming Chen , Chang-Yun Chang
发明人： Feng Yuan , Tsung-Lin Lee , Hung-Ming Chen , Chang-Yun Chang
IPC分类号： H01L21/28
CPC分类号： H01L21/845 , H01L21/76224 , H01L21/823431 , H01L29/66795
摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate including a top surface; forming a first insulation region and a second insulation region in the semiconductor substrate; and recessing the first insulation region and the second insulation region. Top surfaces of remaining portions of the first insulation region and the second insulation region are flat surfaces or divot surfaces. A portion of the semiconductor substrate between and adjoining removed portions of the first insulation region and the second insulation region forms a fin.
摘要翻译：形成集成电路结构的方法包括提供包括顶表面的半导体衬底; 在所述半导体衬底中形成第一绝缘区域和第二绝缘区域; 并使第一绝缘区域和第二绝缘区域凹陷。第一绝缘区域和第二绝缘区域的剩余部分的顶表面是平坦表面或表面。第一绝缘区域和第二绝缘区域的相邻去除部分之间的半导体衬底的一部分形成翅片。

12. 发明授权

US08610240B2 Integrated circuit with multi recessed shallow trench isolation 有权
标题翻译：集成电路具有多凹槽浅沟槽隔离
公开(公告)号：US08610240B2
公开(公告)日：2013-12-17
申请号：US12838264
申请日：2010-07-16
申请人： Tsung-Lin Lee , Chang-Yun Chang
发明人： Tsung-Lin Lee , Chang-Yun Chang
IPC分类号： H01L21/70
CPC分类号： H01L21/762 , H01L21/76232
摘要： A system and method for forming multi recessed shallow trench isolation structures on substrate of an integrated circuit is provided. An integrated circuit includes a substrate, at least two shallow trench isolation (STI) structures formed in the substrate, an oxide fill disposed in the at least two STI structures, and semiconductor devices disposed on the oxide fill in the at least two STI structures. A first STI structure is formed to a first depth and a second STI structure is formed to a second depth. The oxide fill fills the at least two STI structures, and the first depth and the second depth are based on semiconductor device characteristics of semiconductor devices disposed thereon.
摘要翻译：提供了一种用于在集成电路的衬底上形成多凹槽浅沟槽隔离结构的系统和方法。集成电路包括衬底，在衬底中形成的至少两个浅沟槽隔离（STI）结构，设置在至少两个STI结构中的氧化物填充物，以及设置在至少两个STI结构中的氧化物填充物上的半导体器件。第一STI结构形成为第一深度，并且第二STI结构形成为第二深度。氧化物填充物填充至少两个STI结构，并且第一深度和第二深度基于设置在其上的半导体器件的半导体器件特性。

13. 发明授权

US08174073B2 Integrated circuit structures with multiple FinFETs 有权
标题翻译：具有多个FinFET的集成电路结构
公开(公告)号：US08174073B2
公开(公告)日：2012-05-08
申请号：US11807652
申请日：2007-05-30
申请人： Tsung-Lin Lee , Chang-Yun Chang , Sheng-Da Liu , Fu-Liang Yang
发明人： Tsung-Lin Lee , Chang-Yun Chang , Sheng-Da Liu , Fu-Liang Yang
IPC分类号： H01L27/12
CPC分类号： H01L21/823437 , H01L21/823431 , H01L21/845 , H01L27/088 , H01L27/1211 , H01L29/165 , H01L29/41791 , H01L29/66795 , H01L29/7843 , H01L29/7848 , H01L29/785 , H01L29/7851
摘要： A semiconductor structure includes a semiconductor substrate; and a first Fin field-effect transistor (FinFET) and a second FinFET at a surface of the semiconductor substrate. The first FinFET includes a first fin; and a first gate electrode over a top surface and sidewalls of the first fin. The second FinFET includes a second fin spaced apart from the first fin by a fin space; and a second gate electrode over a top surface and sidewalls of the second fin. The second gate electrode is electrically disconnected from the first gate electrode. The first and the second gate electrodes have a gate height greater than about one half of the fin space.
摘要翻译：半导体结构包括半导体衬底; 以及在半导体衬底的表面处的第一Fin场效应晶体管（FinFET）和第二FinFET。第一个FinFET包括第一个鳍; 以及在第一鳍的顶表面和侧壁上的第一栅电极。第二FinFET包括通过鳍片空间与第一鳍片间隔开的第二鳍片; 以及在第二鳍的顶表面和侧壁上的第二栅电极。第二栅电极与第一栅电极电断开。第一和第二栅电极具有大于翅片空间的约一半的栅极高度。

14. 发明申请

US20110084340A1 Voids in STI Regions for Forming Bulk FinFETs 有权
标题翻译：用于形成大量FinFET的STI区域中的空隙
公开(公告)号：US20110084340A1
公开(公告)日：2011-04-14
申请号：US12612442
申请日：2009-11-04
申请人： Feng Yuan , Tsung-Lin Lee , Hung-Ming Chen , Chang-Yun Chang
发明人： Feng Yuan , Tsung-Lin Lee , Hung-Ming Chen , Chang-Yun Chang
IPC分类号： H01L27/088 , H01L21/762
CPC分类号： H01L27/0203 , H01L21/76224 , H01L21/764 , H01L21/823431 , H01L21/823481 , H01L21/845
摘要： An integrated circuit structure includes a substrate; two insulation regions over the substrate, with one of the two insulation regions including a void therein; and a first semiconductor strip between and adjoining the two insulation regions. The first semiconductor strip includes a top portion forming a fin over top surfaces of the two insulation regions.
摘要翻译：集成电路结构包括：基板; 两个绝缘区域在衬底上，两个绝缘区域中的一个在其中包括空隙; 以及在所述两个绝缘区域之间并邻接所述两个绝缘区域的第一半导体条带。第一半导体条包括在两个绝缘区域的顶表面上形成翅片的顶部部分。

15. 发明授权

US08941153B2 FinFETs with different fin heights 有权
标题翻译： FinFET具有不同的翅片高度
公开(公告)号：US08941153B2
公开(公告)日：2015-01-27
申请号：US12871655
申请日：2010-08-30
申请人： Tsung-Lin Lee , Chih Chieh Yeh , Chang-Yun Chang , Feng Yuan
发明人： Tsung-Lin Lee , Chih Chieh Yeh , Chang-Yun Chang , Feng Yuan
IPC分类号： H01L29/76 , H01L21/8234 , H01L27/088 , H01L29/66
CPC分类号： H01L21/823431 , H01L21/266 , H01L21/76224 , H01L21/823437 , H01L21/823481 , H01L27/0886 , H01L27/1104 , H01L27/1116 , H01L29/0649 , H01L29/41791 , H01L29/66795 , H01L29/785
摘要： An integrated circuit structure includes a semiconductor substrate including a first portion in a first device region, and a second portion in a second device region. A first semiconductor fin is over the semiconductor substrate and has a first fin height. A second semiconductor fin is over the semiconductor substrate and has a second fin height. The first fin height is greater than the second fin height.
摘要翻译：集成电路结构包括包括第一器件区域中的第一部分和第二器件区域中的第二部分的半导体衬底。第一半导体鳍片在半导体衬底之上并且具有第一鳍片高度。第二半导体鳍片在半导体衬底之上并且具有第二鳍片高度。第一鳍高度大于第二翅片高度。

16. 发明授权

US08796156B2 Cross OD FinFET patterning 有权
标题翻译：交叉OD FinFET图案化
公开(公告)号：US08796156B2
公开(公告)日：2014-08-05
申请号：US13343586
申请日：2012-01-04
申请人： Ming-Feng Shieh , Tsung-Lin Lee , Chang-Yun Chang
发明人： Ming-Feng Shieh , Tsung-Lin Lee , Chang-Yun Chang
IPC分类号： H01L21/302
CPC分类号： H01L21/823431 , H01L21/845
摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; providing a first lithography mask, a second lithography mask, and a third lithography mask; forming a first mask layer over the semiconductor substrate, wherein a pattern of the first mask layer is defined using the first lithography mask; performing a first etch to the semiconductor substrate to define an active region using the first mask layer; forming a second mask layer having a plurality of mask strips over the semiconductor substrate and over the active region; forming a third mask layer over the second mask layer, wherein a middle portion of the plurality of mask strips is exposed through an opening in the third mask layer, and end portions of the plurality of mask strips are covered by the third mask layer; and performing a second etch to the semiconductor substrate through the opening.
摘要翻译：形成集成电路结构的方法包括提供半导体衬底; 提供第一光刻掩模，第二光刻掩模和第三光刻掩模; 在所述半导体衬底上形成第一掩模层，其中使用所述第一光刻掩模限定所述第一掩模层的图案; 对所述半导体衬底执行第一蚀刻以使用所述第一掩模层限定有源区; 在所述半导体衬底上并在所述有源区上形成具有多个掩模条的第二掩模层; 在所述第二掩模层上形成第三掩模层，其中所述多个掩模条的中间部分通过所述第三掩模层中的开口露出，并且所述多个掩模条的端部被所述第三掩模层覆盖; 以及通过所述开口对所述半导体衬底进行第二蚀刻。

17. 发明授权

US08592918B2 Forming inter-device STI regions and intra-device STI regions using different dielectric materials 有权
标题翻译：使用不同的介电材料形成器件间STI区和器件内部区域
公开(公告)号：US08592918B2
公开(公告)日：2013-11-26
申请号：US12843658
申请日：2010-07-26
申请人： Feng Yuan , Tsung-Lin Lee , Hung-Ming Chen , Chang-Yun Chang
发明人： Feng Yuan , Tsung-Lin Lee , Hung-Ming Chen , Chang-Yun Chang
IPC分类号： H01L21/02
CPC分类号： H01L21/76224 , H01L21/76229 , H01L21/823431 , H01L21/845 , H01L27/0886 , H01L27/1211
摘要： An integrated circuit structure includes a substrate having a first portion in a first device region and a second portion in a second device region; and two insulation regions in the first device region and over the substrate. The two insulation regions include a first dielectric material having a first k value. A semiconductor strip is between and adjoining the two insulation regions, with a top portion of the semiconductor strip forming a semiconductor fin over top surfaces of the two insulation regions. An additional insulation region is in the second device region and over the substrate. The additional insulation region includes a second dielectric material having a second k value greater than the first k value.
摘要翻译：集成电路结构包括具有第一器件区域中的第一部分和第二器件区域中的第二部分的衬底; 以及在第一器件区域和衬底上的两个绝缘区域。两个绝缘区域包括具有第一k值的第一电介质材料。半导体条在两个绝缘区之间并相邻，半导体条的顶部在两个绝缘区的顶表面上形成半导体鳍。另外的绝缘区域位于第二器件区域和衬底之上。附加绝缘区域包括具有大于第一k值的第二k值的第二电介质材料。

18. 发明授权

US08519481B2 Voids in STI regions for forming bulk FinFETs 有权
标题翻译：在STI区域中形成大块FinFET的空隙
公开(公告)号：US08519481B2
公开(公告)日：2013-08-27
申请号：US12612442
申请日：2009-11-04
申请人： Feng Yuan , Tsung-Lin Lee , Hung-Ming Chen , Chang-Yun Chang
发明人： Feng Yuan , Tsung-Lin Lee , Hung-Ming Chen , Chang-Yun Chang
IPC分类号： H01L27/088
CPC分类号： H01L27/0203 , H01L21/76224 , H01L21/764 , H01L21/823431 , H01L21/823481 , H01L21/845
摘要： An integrated circuit structure includes a substrate; two insulation regions over the substrate, with one of the two insulation regions including a void therein; and a first semiconductor strip between and adjoining the two insulation regions. The first semiconductor strip includes a top portion forming a fin over top surfaces of the two insulation regions.
摘要翻译：集成电路结构包括：基板; 两个绝缘区域在衬底上，两个绝缘区域中的一个在其中包括空隙; 以及在所述两个绝缘区域之间并相邻的第一半导体条带。第一半导体条包括在两个绝缘区域的顶表面上形成翅片的顶部部分。

19. 发明授权

US08110466B2 Cross OD FinFET patterning 有权
标题翻译：交叉OD FinFET图案化
公开(公告)号：US08110466B2
公开(公告)日：2012-02-07
申请号：US12843728
申请日：2010-07-26
申请人： Ming-Feng Shieh , Tsung-Lin Lee , Chang-Yun Chang
发明人： Ming-Feng Shieh , Tsung-Lin Lee , Chang-Yun Chang
IPC分类号： H01L21/428
CPC分类号： H01L21/823431 , H01L21/845
摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; providing a first lithography mask, a second lithography mask, and a third lithography mask; forming a first mask layer over the semiconductor substrate, wherein a pattern of the first mask layer is defined using the first lithography mask; performing a first etch to the semiconductor substrate to define an active region using the first mask layer; forming a second mask layer having a plurality of mask strips over the semiconductor substrate and over the active region; forming a third mask layer over the second mask layer, wherein a middle portion of the plurality of mask strips is exposed through an opening in the third mask layer, and end portions of the plurality of mask strips are covered by the third mask layer; and performing a second etch to the semiconductor substrate through the opening.
摘要翻译：形成集成电路结构的方法包括提供半导体衬底; 提供第一光刻掩模，第二光刻掩模和第三光刻掩模; 在所述半导体衬底上形成第一掩模层，其中使用所述第一光刻掩模限定所述第一掩模层的图案; 对所述半导体衬底执行第一蚀刻以使用所述第一掩模层限定有源区; 在所述半导体衬底上并在所述有源区上形成具有多个掩模条的第二掩模层; 在所述第二掩模层上形成第三掩模层，其中所述多个掩模条的中间部分通过所述第三掩模层中的开口露出，并且所述多个掩模条的端部被所述第三掩模层覆盖; 以及通过所述开口对所述半导体衬底进行第二蚀刻。

20. 发明申请

US20110097863A1 Cross OD FinFET Patterning 有权
标题翻译：交叉OD FinFET图案
公开(公告)号：US20110097863A1
公开(公告)日：2011-04-28
申请号：US12843728
申请日：2010-07-26
申请人： Ming-Feng Shieh , Tsung-Lin Lee , Chang-Yun Chang
发明人： Ming-Feng Shieh , Tsung-Lin Lee , Chang-Yun Chang
IPC分类号： H01L21/336
CPC分类号： H01L21/823431 , H01L21/845
摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; providing a first lithography mask, a second lithography mask, and a third lithography mask; forming a first mask layer over the semiconductor substrate, wherein a pattern of the first mask layer is defined using the first lithography mask; performing a first etch to the semiconductor substrate to define an active region using the first mask layer; forming a second mask layer having a plurality of mask strips over the semiconductor substrate and over the active region; forming a third mask layer over the second mask layer, wherein a middle portion of the plurality of mask strips is exposed through an opening in the third mask layer, and end portions of the plurality of mask strips are covered by the third mask layer; and performing a second etch to the semiconductor substrate through the opening.
摘要翻译：形成集成电路结构的方法包括提供半导体衬底; 提供第一光刻掩模，第二光刻掩模和第三光刻掩模; 在所述半导体衬底上形成第一掩模层，其中使用所述第一光刻掩模限定所述第一掩模层的图案; 对所述半导体衬底执行第一蚀刻以使用所述第一掩模层限定有源区; 在所述半导体衬底上并在所述有源区上形成具有多个掩模条的第二掩模层; 在所述第二掩模层上形成第三掩模层，其中所述多个掩模条的中间部分通过所述第三掩模层中的开口露出，并且所述多个掩模条的端部被所述第三掩模层覆盖; 以及通过所述开口对所述半导体衬底进行第二蚀刻。

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