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11. 发明申请

US20100088470A1 OPTIMIZING INFORMATION LIFECYCLE MANAGEMENT FOR FIXED STORAGE 失效
标题翻译：优化信息固定存储的生存管理
公开(公告)号：US20100088470A1
公开(公告)日：2010-04-08
申请号：US12244454
申请日：2008-10-02
申请人： Christopher Lionetti , Sompong Paul Olarig , Vladimir Sadovsky
发明人： Christopher Lionetti , Sompong Paul Olarig , Vladimir Sadovsky
IPC分类号： G06F12/02 , G06F12/08
CPC分类号： G06F3/0632 , G06F3/0605 , G06F3/0616 , G06F3/0649 , G06F3/0689
摘要： The method may query the disk drive for a size where size may be a total number of logical blocks on the disk drive. The drive may receive a size response where the size includes a total number of logical blocks on the disk drive. The number of usage blocks necessary to represent the number of logical blocks on the disk drive may then be determined and usage data may be stored in the usage blocks. The data may be stored in the buffer of the disk drive. The data may also be stored in the DDF of a RAID drive. The data may be used to permit incremental backups of disk drives by backing up only the blocks that are indicated as having been changed. In addition, information about the access to the drive may be collected and stored for later analysis.
摘要翻译：该方法可以查询磁盘驱动器的大小，其大小可以是磁盘驱动器上逻辑块的总数。驱动器可能会收到一个大小响应，其大小包括磁盘驱动器上的逻辑块总数。然后可以确定表示磁盘驱动器上的逻辑块数量所需的使用块的数量，并且可以将使用数据存储在使用块中。数据可能存储在磁盘驱动器的缓冲区中。数据也可以存储在RAID驱动器的DDF中。数据可用于通过仅备份指示为已更改的块来允许磁盘驱动器的增量备份。此外，可以收集和存储有关访问驱动器的信息以供以后分析。

12. 发明授权

US08161251B2 Heterogeneous storage array optimization through eviction 有权
标题翻译：异构存储阵列优化通过驱逐
公开(公告)号：US08161251B2
公开(公告)日：2012-04-17
申请号：US12473225
申请日：2009-05-27
申请人： Nathan Steven Obr , Sompong Paul Olarig , Shiv Rajpal
发明人： Nathan Steven Obr , Sompong Paul Olarig , Shiv Rajpal
IPC分类号： G06F12/00 , G06F12/16
CPC分类号： G06F3/061 , G06F3/0614 , G06F3/0647 , G06F3/068 , G06F12/0246 , G06F2212/7211
摘要： A storage system can comprise storage devices having storage media with differing characteristics. An eviction handler can receive information regarding the state of storage media or of data stored thereon, as well as information regarding application or operating system usage, or expected usage, of data, or information regarding policy, including user-selected policy. Such information can be utilized by the eviction handler to optimize the use of the storage system by evicting data from storage media, including evicting data in order to perform maintenance on, or replace, such storage media, and evicting data to make room for other data, such as data copied to such storage media to facilitate pre-fetching or implement policy. The eviction handler can be implemented by any one or more of processes executing on a computing device, control circuitry of any one or more of the storage devices, or intermediate storage-centric devices.
摘要翻译：存储系统可以包括具有不同特征的存储介质的存储设备。驱逐处理者可以接收关于存储介质或其上存储的数据的状态的信息，以及关于包括用户选择的策略在内的关于策略的数据或有关策略的信息的应用或操作系统使用或预期使用的信息。驱逐处理程序可以利用这种信息来优化存储系统的使用，方法是从存储介质中取出数据，包括逐出数据，以对这些存储介质进行维护或替换，以及驱逐数据为其他数据腾出空间，例如将数据复制到这样的存储介质以便于预取或实现策略。驱逐处理程序可以由在计算设备上执行的任何一个或多个进程，任何一个或多个存储设备的控制电路或中间存储为中心的设备来实现。

13. 发明授权

US07721096B2 Self-authenticating blade server in a secure environment 有权
标题翻译：自我认证的刀片服务器在安全的环境中
公开(公告)号：US07721096B2
公开(公告)日：2010-05-18
申请号：US11346793
申请日：2006-02-03
申请人： Shane Chiasson , Sompong Paul Olarig , Lee Zaretsky
发明人： Shane Chiasson , Sompong Paul Olarig , Lee Zaretsky
IPC分类号： H04L9/00 , H04L9/32
CPC分类号： G06F21/6245 , G06F2221/2105 , G06F2221/2129 , G06F2221/2149 , H04L9/3247 , H04L2209/127
摘要： A blade server module in an information handling system may have secure environment and authorized removal modes in non-volatile memory. If the secure environment mode is set in the blade server module, then the authorized removal mode is read to determine whether it also is set. If both of these modes are set then authentication keys of the inserted blade server module and blade server chassis are verified as being properly associated. If the authorized removal mode is not set when the blade server module is inserted into a server chassis or authentication keys are not verified as being properly associated then the blade server module power-up sequence is disabled. The authentication keys may be administrator/user defined. The secure environment and authorized removal modes may be set and cleared by the administrator/user.
摘要翻译：信息处理系统中的刀片服务器模块可以在非易失性存储器中具有安全的环境和授权的移除模式。如果在刀片服务器模块中设置了安全环境模式，则读取授权的删除模式以确定是否也设置了该模式。如果设置了这两种模式，则插入的刀片服务器模块和刀片服务器机箱的认证密钥将被验证为正确关联。如果将刀片式服务器模块插入服务器机箱中没有设置授权删除模式，或认证键未被验证为正确关联，则刀片服务器模块上电序列将被禁用。认证密钥可以是管理员/用户定义的。安全环境和授权的删除模式可以由管理员/用户设置和清除。

14. 发明授权

US06223239B1 Dual purpose apparatus, method and system for accelerated graphics port or system area network interface 失效
标题翻译：用于加速图形端口或系统区域网络接口的双重目的设备，方法和系统
公开(公告)号：US06223239B1
公开(公告)日：2001-04-24
申请号：US09133788
申请日：1998-08-12
申请人： Sompong Paul Olarig
发明人： Sompong Paul Olarig
IPC分类号： G06F1300
CPC分类号： G06F13/387
摘要： A multiple use core logic chipset is provided in a computer system that may be configured either as a bridge between an accelerated graphics port (“AGP”) bus and host and memory buses, or as a bridge between a system area network interface and the host bus and the system memory bus. The function of the multiple use chipset is determined at the time of manufacture of the computer system, or in the field whether an AGP bus bridge or a system area network interface is to be implemented. Selection of the type of bus bridge (AGP or system area network interface) in the multiple use core logic chipset may be implemented by a hardware signal input, or by software during computer system configuration or power on self test (“POST”). Software configuration may also be determined upon detection of either an AGP device or a system area network interface connected to the core logic chipset.
摘要翻译：在可以配置为加速图形端口（“AGP”）总线与主机与存储器总线之间的桥的计算机系统中提供多用核心逻辑芯片组，或作为系统区域网络接口和主机之间的桥总线和系统内存总线。多用途芯片组的功能在计算机系统制造时确定，或在现场确定是否实现AGP总线桥接器或系统区域网络接口。可以通过硬件信号输入或计算机系统配置或上电自检（“POST”）期间的软件来实现多用途核心逻辑芯片组中的总线桥（AGP或系统区域网络接口）类型的选择。还可以在检测到AGP设备或连接到核心逻辑芯片组的系统区域网络接口时确定软件配置。

15. 发明授权

US5841795A Error correction codes 失效
标题翻译：纠错码
公开(公告)号：US5841795A
公开(公告)日：1998-11-24
申请号：US599757
申请日：1996-02-12
申请人： Sompong Paul Olarig , William L. Walker
发明人： Sompong Paul Olarig , William L. Walker
IPC分类号： G06F11/10 , G11C29/00
CPC分类号： G06F11/1016 , G06F11/1028
摘要： A method of detecting and correcting errors in a memory subsystem of a computer is described. The method includes beginning a write operation of N data bits to a memory, generating M check bits from the N data bits, writing the N data bits and the M check bits to the memory, reading the N data bits and M check bits from the memory, generating X syndrome bits from the N data bits and the M check bits, and using the X syndrome bits to detect and correct errors. Preferably, the M check bits are generated also from A address bits corresponding to the location in memory to which the N data bits and M check bits are to be written.
摘要翻译：描述了一种检测和校正计算机的存储器子系统中的错误的方法。该方法包括开始对存储器进行N个数据位的写操作，从N个数据位产生M个校验位，将N个数据位和M个校验位写入存储器，读取N个数据位和M个校验位存储器，从N个数据位和M个校验位生成X个校正子位，并使用X校验位来检测和校正错误。优选地，也可以从对应于要写入N个数据位和M个校验位的存储器中的位置的A地址位产生M个校验位。

16. 发明授权

US09110783B1 Application-transparent hybridized caching for high-performance storage 有权
标题翻译：应用透明的混合缓存，用于高性能存储
公开(公告)号：US09110783B1
公开(公告)日：2015-08-18
申请号：US13618851
申请日：2012-09-14
申请人： Kushagra Vaid , Sompong Paul Olarig
发明人： Kushagra Vaid , Sompong Paul Olarig
IPC分类号： G06F12/00 , G06F12/02 , G11C16/10
CPC分类号： G06F3/061 , G06F3/0655 , G06F3/0685 , G06F3/0688 , G06F12/0246 , G06F12/0871 , G06F12/0893 , G06F2212/1016 , G06F2212/2146 , G06F2212/217 , G06F2212/225 , G06F2212/312 , G11C7/1072 , G11C11/40615 , G11C16/102
摘要： Systems, apparatus, and computer-implemented methods are provided for the hybridization of cache memory utilizing both magnetic and solid-state memory media. A solid-state cache controller apparatus can be coupled to a host computing system to maximize efficiency of the system in a manner that is transparent to the high-level applications using the system. The apparatus includes an associative memory component and a solid-state cache control component. Solid-state memory is configured to store data blocks of host read operations. If a host-read operation is requested, the controller communicates with a solid-state cache memory controller to determine whether a tag array data structure indicates a cached copy of the requested data block is available in solid-state memory.
摘要翻译：提供了系统，装置和计算机实现的方法，用于使用磁性和固态存储介质的高速缓冲存储器的杂交。固态高速缓存控制器设备可以耦合到主机计算系统，以对使用该系统的高级应用是透明的方式来最大化系统的效率。该装置包括关联存储器组件和固态高速缓存控制组件。固态存储器被配置为存储主机读取操作的数据块。如果请求主机读取操作，则控制器与固态缓存存储器控制器进行通信，以确定标签阵列数据结构是否指示所请求数据块的缓存副本在固态存储器中可用。

17. 发明授权

US06175889B1 Apparatus, method and system for a computer CPU and memory to high speed peripheral interconnect bridge having a plurality of physical buses with a single logical bus number 有权
标题翻译：具有计算机CPU和存储器的装置，方法和系统，具有具有单个逻辑总线号的多个物理总线的高速外围设备互连桥
公开(公告)号：US06175889B1
公开(公告)日：2001-01-16
申请号：US09177441
申请日：1998-10-21
申请人： Sompong Paul Olarig
发明人： Sompong Paul Olarig
IPC分类号： G06F1340
CPC分类号： G06F13/4027
摘要： A core logic chip set in a computer system provides a bridge between processor host and memory buses and a plurality of registered peripheral component interconnect (“PCI-X”) buses capable of operating at 66 MHz. Each of the plurality of PCI-X buses have the same logical bus number. The core logic chip set has an arbiter having Request (“REQ”) and Grant (“GNT”) signal lines for each PCI-X device connected to the plurality of PCI-X physical buses. Each of the plurality of PCI-X buses has its own read and write queues to provide transaction concurrency of PCI-X devices on different ones of the plurality of PCI-X buses when the transaction addresses are not the same or are M byte aligned. Upper and lower memory address range registers store upper and lower memory addresses associated with each PCI-X device. Whenever a transaction occurs, the transaction address is compared with the stored range of memory addresses. If a match between addresses is found then strong ordering is used. If no match is found then weak ordering may be used to improve transaction latency times. PCI-X device to PCI-X device transactions may occur without being starved by CPU host bus to PCI-X bus transactions.
摘要翻译：计算机系统中的核心逻辑芯片组提供处理器主机和存储器总线之间的桥接以及能够以66MHz操作的多个注册的外围组件互连（“PCI-X”）总线。多个PCI-X总线中的每一个具有相同的逻辑总线号。核心逻辑芯片组具有针对连接到多个PCI-X物理总线的每个PCI-X设备的请求（“REQ”）和Grant（“GNT”）信号线的仲裁器。多个PCI-X总线中的每一个具有其自己的读和写队列，以在交易地址不相同或是M字节对齐时提供PCI-X总线上不同的PCI-X总线上的PCI-X设备的事务并发。上下存储器地址范围寄存器存储与每个PCI-X设备相关联的上部和下部存储器地址。每当事务发生时，将交易地址与存储的存储器地址范围进行比较。如果发现地址之间的匹配，则使用强排序。如果没有找到匹配，则可以使用弱排序来提高事务延迟时间。 PCI-X设备到PCI-X设备事务可能不会被CPU主机总线饿死到PCI-X总线事务。

18. 发明授权

US6041377A Method and apparatus for distributing interrupts in a scalable symmetric multiprocessor system without changing the bus width or bus protocol 有权
标题翻译：用于在可扩展的对称多处理器系统中分配中断而不改变总线宽度或总线协议的方法和装置
公开(公告)号：US6041377A
公开(公告)日：2000-03-21
申请号：US243235
申请日：1999-02-02
申请人： Dale J. Mayer , Sompong Paul Olarig , William F. Whiteman , David F. Heinrich
发明人： Dale J. Mayer , Sompong Paul Olarig , William F. Whiteman , David F. Heinrich
IPC分类号： G06F13/18 , G06F13/24 , G06F13/362 , G06F13/00
CPC分类号： G06F13/24
摘要： A method for supporting multiple distributed interrupt controllers, designated as bus agents, in a symmetric multiprocessing system, which method includes the steps of assigning a unique identification number to each bus agent, receiving bus requests from the bus agents over four data lines in groups of four, and granting bus ownership to a selected one of the requesting bus agents. Similarly, a computer system that supports multiple distributed interrupt controllers, designated as bus agents, in a symmetric multiprocessing system, which computer system includes structure for assigning a unique identification number to each bus agent, four data lines for receiving bus requests from the bus agents in groups of four, and structure for granting bus ownership to a selected one of the requesting bus agents.
摘要翻译：一种用于在对称多处理系统中支持指定为总线代理的多个分布式中断控制器的方法，该方法包括以下步骤：为每个总线代理分配唯一的标识号，从四个数据线上接收来自总线代理的总线请求，四，并向所选择的一个请求巴士代理人授予公共汽车所有权。类似地，一种计算机系统，其支持在对称多处理系统中指定为总线代理的多个分布式中断控制器，该计算机系统包括用于向每个总线代理分配唯一标识号的结构，用于从总线代理接收总线请求的四个数据线以四组为单位，以及将公交车所有权授予选定的一个请求巴士代理人的结构。

19. 发明授权

US5859989A Apparatus method and system for 64 bit peripheral component interconnect bus using accelerated graphics port logic circuits 失效
标题翻译：使用加速图形端口逻辑电路的64位外设组件互连总线的装置方法和系统
公开(公告)号：US5859989A
公开(公告)日：1999-01-12
申请号：US855341
申请日：1997-05-13
申请人： Sompong Paul Olarig , Ronald Timothy Horan
发明人： Sompong Paul Olarig , Ronald Timothy Horan
IPC分类号： G06T11/00 , G06T13/00
CPC分类号： G06T11/00
摘要： A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ("AGP") bus and host and memory buses, as a bridge between a 64 bit additional peripheral component interconnect ("PCI") bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional PCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an additional 64 bit PCI bus bridge is to be implemented. The multiple use core logic chip set has an arbiter having Request ("REQ") and Grant ("GNT") signal lines for each PCI device utilized on the additional 64 bit PCI bus. Selection of the type of bus bridge (AGP or PCI) in the multiple use core logic chip set may be made by a hardware signal input, or by software during computer system configuration or power on self test ("POST"). Software configuration may also be determined upon detection of a PCI device connected to the common bus.
摘要翻译：在可以配置为加速图形端口（“AGP”）总线和主机与存储器总线之间的桥接器的计算机系统中提供了多用途核心逻辑芯片组，作为64位附加外围组件互连 “PCI”）总线和主机和存储器总线，或作为主PCI总线和附加PCI总线之间的桥梁。多个使用芯片组的功能在计算机系统的制造时或在现场确定是否要实现AGP总线桥接器或附加的64位PCI总线桥接器。多用核心逻辑芯片组具有对在额外的64位PCI总线上使用的每个PCI设备的请求（“REQ”）和Grant（“GNT”）信号线的仲裁器。在多用途核心逻辑芯片组中选择总线桥（AGP或PCI）的类型可以通过硬件信号输入，或者在计算机系统配置或上电自检（“POST”）期间由软件进行。在检测到连接到公共总线的PCI设备时也可以确定软件配置。

20. 发明授权

US08386727B2 Supporting interleaved read/write operations from/to multiple target devices 有权
公开(公告)号：US08386727B2
公开(公告)日：2013-02-26
申请号：US10039010
申请日：2001-12-31
申请人： Sompong Paul Olarig , Pamela M. Cook
发明人： Sompong Paul Olarig , Pamela M. Cook
IPC分类号： G06F12/00 , G06F12/14 , G06F13/00 , G06F13/28
CPC分类号： G06F13/4221 , G06F12/0607 , G06F2213/0024
摘要： Bus transactions in a computer network are improved by utilizing a multicast transaction from a single initiator to multiple targets. The multiple targets simultaneously execute the transaction and provide a return transaction to the initiator. The transaction cycle time is reduced as individual request to each target is replace with a single request to a collective target group, addressable by a single base memory address. Interleaved read or write operation is provided to allow the multiple targets of a particular target group to independently execute a portion of the transaction request. Improved bus performance is achieve by utilizing the higher throughput capacity of the system bus providing a higher number of shorter data segments from each target executing its portion of the larger transaction.

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