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11. 发明申请

US20100190319A1 METHOD OF FORMING MEMORY WITH FLOATING GATES INCLUDING SELF-ALIGNED METAL NANODOTS USING A COUPLING LAYER 有权
标题翻译：使用耦合层形成包含自对准金属纳米线的浮动栅的存储器的方法
公开(公告)号：US20100190319A1
公开(公告)日：2010-07-29
申请号：US12754408
申请日：2010-04-05
申请人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai , Tuan D. Pham
发明人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai , Tuan D. Pham
IPC分类号： H01L21/28
CPC分类号： H01L21/28273 , B82Y10/00 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42332 , Y10S438/962 , Y10S977/72 , Y10S977/81 , Y10S977/943
摘要： Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, a coupling layer such as an amino functional silane group is provided on a gate oxide layer on a substrate. The substrate is dip coated in a colloidal solution having metal nanodots, causing the nanodots to attach to sites in the coupling layer. The coupling layer is then dissolved such as by rinsing or nitrogen blow drying, leaving the nanodots on the gate oxide layer. The nanodots react with the coupling layer and become negatively charged and arranged in a uniform monolayer, repelling a deposition of an additional monolayer of nanodots. In a configuration using a control gate over a high-k dielectric floating gate which includes the nanodots, the control gates may be separated by etching while the floating gate dielectric extends uninterrupted since the nanodots are electrically isolated from one another.
摘要翻译：提供了用于制造具有金属纳米点作为电荷存储元件的存储器的技术。在示例性方法中，在基板上的栅极氧化物层上提供诸如氨基官能的硅烷基团之类的耦合层。将基底浸渍在具有金属纳米点的胶体溶液中，使得纳米点附着到偶联层中的位置。然后通过漂洗或氮吹干燥将溶剂层溶解，将纳米点留在栅极氧化物层上。纳米点与偶联层反应并变成负电荷并排列成均匀的单层，排斥另外的单层纳米点的沉积。在使用包括纳米点的高k电介质浮动栅极上的控制栅极的配置中，可以通过蚀刻来分离控制栅极，同时浮栅绝缘体不间断延伸，因为纳米点彼此电隔离。

12. 发明授权

US07615447B2 Composite charge storage structure formation in non-volatile memory using etch stop technologies 有权
标题翻译：使用蚀刻停止技术在非易失性存储器中形成复合电荷存储结构
公开(公告)号：US07615447B2
公开(公告)日：2009-11-10
申请号：US11960498
申请日：2007-12-19
申请人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai
发明人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L29/42324 , H01L29/7881
摘要： Semiconductor-based non-volatile memory that includes memory cells with composite charge storage elements is fabricated using an etch stop layer during formation of at least a portion of the storage element. One composite charge storage element suitable for memory applications includes a first charge storage region having a larger gate length or dimension in a column direction than a second charge storage region. While not required, the different regions can be formed of the same or similar materials, such as polysilicon. Etching a second charge storage layer selectively with respect to a first charge storage layer can be performed using an interleaving etch-stop layer. The first charge storage layer is protected from overetching or damage during etching of the second charge storage layer. Consistency in the dimensions of the individual memory cells can be increased.
摘要翻译：包括具有复合电荷存储元件的存储器单元的基于半导体的非易失性存储器在形成存储元件的至少一部分期间使用蚀刻停止层制造。适用于存储器应用的一个复合电荷存储元件包括具有比第二电荷存储区域在列方向上更大的栅极长度或尺寸的第一电荷存储区域。虽然不需要，但是不同的区域可以由相同或相似的材料形成，例如多晶硅。可以使用交错蚀刻停止层来执行相对于第一电荷存储层选择性地蚀刻第二电荷存储层。第一电荷存储层在第二电荷存储层的蚀刻期间被保护以免过蚀或损坏。可以增加各个存储单元尺寸的一致性。

13. 发明申请

US20090163009A1 Composite Charge Storage Structure Formation In Non-Volatile Memory Using Etch Stop Technologies 有权
标题翻译：使用蚀刻停止技术在非易失性存储器中的复合电荷存储结构形成
公开(公告)号：US20090163009A1
公开(公告)日：2009-06-25
申请号：US11960498
申请日：2007-12-19
申请人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai
发明人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai
IPC分类号： H01L21/28
CPC分类号： H01L27/11521 , H01L29/42324 , H01L29/7881
摘要： Semiconductor-based non-volatile memory that includes memory cells with composite charge storage elements is fabricated using an etch stop layer during formation of at least a portion of the storage element. One composite charge storage element suitable for memory applications includes a first charge storage region having a larger gate length or dimension in a column direction than a second charge storage region. While not required, the different regions can be formed of the same or similar materials, such as polysilicon. Etching a second charge storage layer selectively with respect to a first charge storage layer can be performed using an interleaving etch-stop layer. The first charge storage layer is protected from overetching or damage during etching of the second charge storage layer. Consistency in the dimensions of the individual memory cells can be increased.
摘要翻译：包括具有复合电荷存储元件的存储器单元的基于半导体的非易失性存储器在形成存储元件的至少一部分期间使用蚀刻停止层制造。适用于存储器应用的一个复合电荷存储元件包括具有比第二电荷存储区域在列方向上更大的栅极长度或尺寸的第一电荷存储区域。虽然不需要，但是不同的区域可以由相同或相似的材料形成，例如多晶硅。可以使用交错蚀刻停止层来执行相对于第一电荷存储层选择性地蚀刻第二电荷存储层。第一电荷存储层在第二电荷存储层的蚀刻期间被保护以免过蚀或损坏。可以增加各个存储单元尺寸的一致性。

14. 发明授权

US08222091B2 Damascene method of making a nonvolatile memory device 有权
标题翻译：制作非易失性存储器件的镶嵌方法
公开(公告)号：US08222091B2
公开(公告)日：2012-07-17
申请号：US13309857
申请日：2011-12-02
申请人： Vinod Robert Purayath , George Matamis , James Kai , Takashi Orimoto
发明人： Vinod Robert Purayath , George Matamis , James Kai , Takashi Orimoto
IPC分类号： H01L21/82
CPC分类号： H01L27/101 , H01L27/1021
摘要： A method of making a device includes providing a first device level containing first semiconductor rails separated by first insulating features, forming a sacrificial layer over the first device level, patterning the sacrificial layer and the first semiconductor rails in the first device level to form a plurality of second rails extending in a second direction, wherein the plurality of second rails extend at least partially into the first device level and are separated from each other by rail shaped openings which extend at least partially into the first device level, forming second insulating features between the plurality of second rails, removing the sacrificial layer, and forming second semiconductor rails between the second insulating features in a second device level over the first device level. The first semiconductor rails extend in a first direction. The second semiconductor rails extend in the second direction different from the first direction.
摘要翻译：一种制造器件的方法包括提供包含由第一绝缘特征分开的第一半导体轨道的第一器件电平，在第一器件电平上形成牺牲层，在第一器件电平图形化牺牲层和第一半导体轨道以形成多个的第二轨道，其沿着第二方向延伸，其中所述多个第二轨道至少部分地延伸到所述第一装置水平面并且通过至少部分地延伸到所述第一装置水平的轨道形开口彼此分开，所述多个第二轨道，去除所述牺牲层，以及在所述第二设备水平上的第二设备水平的所述第二绝缘特征之间形成第二半导体轨道。第一半导体轨道沿第一方向延伸。第二半导体轨道沿与第一方向不同的第二方向延伸。

15. 发明授权

US07888210B2 Non-volatile memory fabrication and isolation for composite charge storage structures 有权
标题翻译：用于复合电荷存储结构的非易失性存储器制造和隔离
公开(公告)号：US07888210B2
公开(公告)日：2011-02-15
申请号：US11960518
申请日：2007-12-19
申请人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai
发明人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： Fabricating semiconductor-based non-volatile memory that includes composite storage elements, such as those with first and second charge storage regions, can include etching more than one charge storage layer. To avoid inadvertent shorts between adjacent storage elements, a first charge storage layer for a plurality of non-volatile storage elements is formed into rows prior to depositing the second charge storage layer. Sacrificial features can be formed between the rows of the first charge storage layer that are adjacent in a column direction, before or after forming the rows of the first charge layer. After forming interleaving rows of the sacrificial features and the first charge storage layer, the second charge storage layer can be formed. The layers can then be etched into columns and the substrate etched to form isolation trenches between adjacent columns. The second charge storage layer can then be etched to form the second charge storage regions for the storage elements.
摘要翻译：制造包括诸如具有第一和第二电荷存储区域的那些的复合存储元件的基于半导体的非易失性存储器可以包括蚀刻多于一个电荷存储层。为了避免相邻存储元件之间的意外短路，在沉积第二电荷存储层之前，用于多个非易失性存储元件的第一电荷存储层形成为行。可以在形成第一电荷层的行之前或之后，在列方向上相邻的第一电荷存储层的行之间形成牺牲特征。在形成牺牲特征和第一电荷存储层的交错行之后，可以形成第二电荷存储层。然后可以将这些层蚀刻成柱，并且蚀刻衬底以在相邻柱之间形成隔离沟槽。然后可以蚀刻第二电荷存储层以形成用于存储元件的第二电荷存储区域。

16. 发明申请

US20090162977A1 Non-Volatile Memory Fabrication And Isolation For Composite Charge Storage Structures 有权
标题翻译：用于复合电荷存储结构的非易失性存储器制造和隔离
公开(公告)号：US20090162977A1
公开(公告)日：2009-06-25
申请号：US11960518
申请日：2007-12-19
申请人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai
发明人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： Fabricating semiconductor-based non-volatile memory that includes composite storage elements, such as those with first and second charge storage regions, can include etching more than one charge storage layer. To avoid inadvertent shorts between adjacent storage elements, a first charge storage layer for a plurality of non-volatile storage elements is formed into rows prior to depositing the second charge storage layer. Sacrificial features can be formed between the rows of the first charge storage layer that are adjacent in a column direction, before or after forming the rows of the first charge layer. After forming interleaving rows of the sacrificial features and the first charge storage layer, the second charge storage layer can be formed. The layers can then be etched into columns and the substrate etched to form isolation trenches between adjacent columns. The second charge storage layer can then be etched to form the second charge storage regions for the storage elements.
摘要翻译：制造包括诸如具有第一和第二电荷存储区域的那些的复合存储元件的基于半导体的非易失性存储器可以包括蚀刻多于一个电荷存储层。为了避免相邻存储元件之间的意外短路，在沉积第二电荷存储层之前，用于多个非易失性存储元件的第一电荷存储层形成为行。可以在形成第一电荷层的行之前或之后，在列方向上相邻的第一电荷存储层的行之间形成牺牲特征。在形成牺牲特征和第一电荷存储层的交错行之后，可以形成第二电荷存储层。然后可以将这些层蚀刻成柱，并且蚀刻衬底以在相邻柱之间形成隔离沟槽。然后可以蚀刻第二电荷存储层以形成用于存储元件的第二电荷存储区域。

17. 发明申请

US20090155967A1 METHOD OF FORMING MEMORY WITH FLOATING GATES INCLUDING SELF-ALIGNED METAL NANODOTS USING A COUPLING LAYER 有权
标题翻译：使用耦合层形成包含自对准金属纳米线的浮动栅的存储器的方法
公开(公告)号：US20090155967A1
公开(公告)日：2009-06-18
申请号：US11958941
申请日：2007-12-18
申请人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai , Tuan D. Pham
发明人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai , Tuan D. Pham
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , B82Y10/00 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42332 , Y10S438/962 , Y10S977/72 , Y10S977/81 , Y10S977/943
摘要： Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, a coupling layer such as an amino functional silane group is provided on a gate oxide layer on a substrate. The substrate is dip coated in a colloidal solution having metal nanodots, causing the nanodots to attach to sites in the coupling layer. The coupling layer is then dissolved such as by rinsing or nitrogen blow drying, leaving the nanodots on the gate oxide layer. The nanodots react with the coupling layer and become negatively charged and arranged in a uniform monolayer, repelling a deposition of an additional monolayer of nanodots. In a configuration using a control gate over a high-k dielectric floating gate which includes the nanodots, the control gates may be separated by etching while the floating gate dielectric extends uninterrupted since the nanodots are electrically isolated from one another.
摘要翻译：提供了用于制造具有金属纳米点作为电荷存储元件的存储器的技术。在示例性方法中，在基板上的栅极氧化物层上提供诸如氨基官能的硅烷基团之类的耦合层。将基底浸渍在具有金属纳米点的胶体溶液中，使得纳米点附着到偶联层中的位置。然后通过漂洗或氮吹干燥将溶剂层溶解，将纳米点留在栅极氧化物层上。纳米点与偶联层反应并变成负电荷并排列成均匀的单层，排斥另外的单层纳米点的沉积。在使用包括纳米点的高k电介质浮动栅极上的控制栅极的配置中，可以通过蚀刻来分离控制栅极，同时浮栅绝缘体不间断延伸，因为纳米点彼此电隔离。

18. 发明授权

US08383479B2 Integrated nanostructure-based non-volatile memory fabrication 有权
公开(公告)号：US08383479B2
公开(公告)日：2013-02-26
申请号：US12840081
申请日：2010-07-20
申请人： Vinod Robert Purayath , James K. Kai , Masaaki Higashitani , Takashi Orimoto , George Matamis , Henry Chien
发明人： Vinod Robert Purayath , James K. Kai , Masaaki Higashitani , Takashi Orimoto , George Matamis , Henry Chien
IPC分类号： H01L21/8247
CPC分类号： H01L21/76224 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L27/11526 , H01L27/11529 , H01L27/11536 , H01L27/11546 , H01L27/11573 , H01L29/788 , Y10S438/962 , Y10S977/774 , Y10S977/936
摘要： Nanostructure-based charge storage regions are included in non-volatile memory devices and integrated with the fabrication of select gates and peripheral circuitry. One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating.

19. 发明授权

US08207036B2 Method for forming self-aligned dielectric cap above floating gate 有权
标题翻译：在浮动栅上形成自对准电介质盖的方法
公开(公告)号：US08207036B2
公开(公告)日：2012-06-26
申请号：US12242857
申请日：2008-09-30
申请人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , Henry Chien , James K. Kai
发明人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , Henry Chien , James K. Kai
IPC分类号： H01L21/336 , H01L21/8238 , H01L21/3205 , H01L21/4763 , H01L29/788
CPC分类号： H01L21/28273 , H01L27/11519 , H01L27/11521 , H01L29/513 , H01L29/7881
摘要： A method for fabricating a non-volatile storage element. The method comprises forming a layer of polysilicon floating gate material over a substrate and forming a layer of nitride at the surface of the polysilicon floating gate material. Floating gates are formed from the polysilicon floating gate material. Individual dielectric caps are formed from the nitride such that each individual nitride dielectric cap is self-aligned with one of the plurality of floating gates. An inter-gate dielectric layer is formed over the surface of the dielectric caps and the sides of the floating gates. Control gates are then formed with the inter-gate dielectric layer separating the control gates from the floating gates. The layer of nitride may be formed using SPA (slot plane antenna) nitridation. The layer of nitride may be formed prior to or after etching of the polysilicon floating gate material to form floating gates.
摘要翻译：一种用于制造非易失性存储元件的方法。该方法包括在衬底上形成多晶硅浮栅材料层，并在多晶硅浮栅材料的表面形成一层氮化物。浮栅由多晶硅浮栅材料形成。各个绝缘盖由氮化物形成，使得每个单独的氮化物介电帽与多个浮动栅之一自对准。在电介质盖的表面和浮动栅极的侧面上形成栅极间介电层。然后，栅极介电层与控制栅极与浮动栅极分离形成控制栅极。可以使用SPA（槽平面天线）氮化形成氮化物层。可以在蚀刻多晶硅浮栅材料之前或之后形成氮化物层以形成浮栅。

20. 发明申请

US20100081267A1 METHOD FOR FORMING SELF-ALIGNED DIELECTRIC CAP ABOVE FLOATING GATE 有权
标题翻译：在浮动门上形成自对准电介质盖的方法
公开(公告)号：US20100081267A1
公开(公告)日：2010-04-01
申请号：US12242857
申请日：2008-09-30
申请人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , Henry Chien , James K. Kai
发明人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , Henry Chien , James K. Kai
IPC分类号： H01L21/3205
CPC分类号： H01L21/28273 , H01L27/11519 , H01L27/11521 , H01L29/513 , H01L29/7881
摘要： A method for fabricating a non-volatile storage element. The method comprises forming a layer of polysilicon floating gate material over a substrate and forming a layer of nitride at the surface of the polysilicon floating gate material. Floating gates are formed from the polysilicon floating gate material. Individual dielectric caps are formed from the nitride such that each individual nitride dielectric cap is self-aligned with one of the plurality of floating gates. An inter-gate dielectric layer is formed over the surface of the dielectric caps and the sides of the floating gates. Control gates are then formed with the inter-gate dielectric layer separating the control gates from the floating gates. The layer of nitride may be formed using SPA (slot plane antenna) nitridation. The layer of nitride may be formed prior to or after etching of the polysilicon floating gate material to form floating gates.
摘要翻译：一种用于制造非易失性存储元件的方法。该方法包括在衬底上形成多晶硅浮栅材料层，并在多晶硅浮栅材料的表面形成一层氮化物。浮栅由多晶硅浮栅材料形成。各个绝缘盖由氮化物形成，使得每个单独的氮化物介电帽与多个浮动栅之一自对准。在电介质盖的表面和浮动栅极的侧面上形成栅极间介电层。然后，栅极介电层与控制栅极与浮动栅极分离形成控制栅极。可以使用SPA（槽平面天线）氮化形成氮化物层。可以在蚀刻多晶硅浮栅材料之前或之后形成氮化物层以形成浮栅。

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