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11. 发明授权

US06349098B1 Method and apparatus for forming a virtual circuit 失效
标题翻译：用于形成虚拟电路的方法和装置
公开(公告)号：US06349098B1
公开(公告)日：2002-02-19
申请号：US09062301
申请日：1998-04-17
申请人： Bidyut Parruck , Makarand Dharmapurikar , Uday Govind Joshi
发明人： Bidyut Parruck , Makarand Dharmapurikar , Uday Govind Joshi
IPC分类号： H04L1256
CPC分类号： H04Q11/0478 , H04L2012/563 , H04L2012/5632
摘要： An improved method and apparatus for automatically forming a virtual circuit in an ATM switch is disclosed. In one aspect of the invention, the virtual circuit may be used to transport an ATM data cell included in an associated communication session. The disclosed method includes the following operative steps. First, a configuration cell is created. Next the virtual circuit is formed by passing the configuration cell to a destination node by way of at least one connective node. The configuration cell updates and validates an associated connection table capable of defining a virtual link. The virtual link being part of the virtual circuit.
摘要翻译：公开了一种用于在ATM交换机中自动形成虚拟电路的改进方法和装置。在本发明的一个方面，虚拟电路可以用于传输包括在相关联的通信会话中的ATM数据单元。所公开的方法包括以下操作步骤。首先，创建一个配置单元。接下来，通过至少一个连接节点将配置单元传递到目的地节点来形成虚拟电路。配置单元更新并验证能够定义虚拟链路的关联连接表。虚拟链路是虚拟电路的一部分。

12. 发明授权

US5257261A Methods and apparatus for concatenating a plurality of lower level SONET signals into higher level sonet signals 失效
标题翻译：将多个较低级SONET信号并入更高级的sonet信号的方法和装置
公开(公告)号：US5257261A
公开(公告)日：1993-10-26
申请号：US877653
申请日：1992-05-01
申请人： Bidyut Parruck , Robert W. Hamlin, Jr.
发明人： Bidyut Parruck , Robert W. Hamlin, Jr.
IPC分类号： G06F5/10 , G06F5/12 , H04J3/06 , H04J3/07 , H04J3/16 , H04L25/05 , H04J14/08
CPC分类号： G06F5/12 , H04J3/0623 , H04J3/076 , H04J3/1611 , H04L25/05 , G06F2205/123
摘要： Apparatus and methods for concatenating a plurality of lower level SONET signals into higher level SONET signals are provided. In generating a higher level SONET signal (e.g., STS-12C) using a plurality of lower level SONET signal processing apparatus (e.g., STS-3 type terminators), the J1 bytes of each lower level signal are tracked through the FIFOs of the apparatus to provide J1 byte control signals, and a logic circuit is provided having phase 3 of the outgoing STS-3 clock, and the J1 byte control signals from all the STS channels of the higher level signal as inputs. The J1 byte control signals from all the channels are combined as a J1ANDcomposite by utilizing a single bus which is coupled to each of the apparatus. The logic circuit inhibits a read of a J1 byte from any particular FIFO unless the J1ANDcomposite signal is high at phase 3 of the clock. In addition to the J1 byte circuitry, the lower level SONET signal processing apparatus are coupled to adjacent apparatus so that the B3 parity byte value from one apparatus is passed to the next apparatus for inclusion in its calculation of the B3 parity byte. Eventually, the master apparatus calculates a B3 parity byte for the STS-Nc signal. The master apparatus also provides the slave apparatus with transmit and receive SPE signals, and a receive J1 signal.
摘要翻译：提供了将多个较低级SONET信号并入更高级SONET信号的装置和方法。在使用多个较低级SONET信号处理装置（例如，STS-3型终端装置）生成较高级别的SONET信号（例如，STS-12C）时，通过装置的FIFO追踪每个下位信号的J1字节提供J1字节控制信号，并且提供具有输出STS-3时钟的相位3的逻辑电路和来自较高电平信号的所有STS通道的J1字节控制信号作为输入。来自所有通道的J1字节控制信号通过利用耦合到每个装置的单个总线作为J1ANDcomposite组合。逻辑电路禁止从任何特定FIFO读取J1字节，除非J1ANDcomposite信号在时钟的相位3处为高电平。除了J1字节电路之外，较低级别的SONET信号处理装置耦合到相邻装置，使得来自一个装置的B3奇偶校验字节值被传递给下一个装置，以包括在其B3奇偶校验字节的计算中。最终，主设备计算STS-Nc信号的B3奇偶校验字节。主设备还向从设备提供发送和接收SPE信号以及接收J1信号。

13. 发明授权

US5870441A Distributed clocking system 失效
标题翻译：分布式计时系统
公开(公告)号：US5870441A
公开(公告)日：1999-02-09
申请号：US918006
申请日：1997-08-25
申请人： John M. Cotton , Nicholas Necula , Bidyut Parruck , Fryderyk Tyra , Alex T. Wissink , Enrique Abreu
发明人： John M. Cotton , Nicholas Necula , Bidyut Parruck , Fryderyk Tyra , Alex T. Wissink , Enrique Abreu
IPC分类号： G06F1/04 , G06F1/08 , H04J3/06 , H04L7/033 , A04L7/00
CPC分类号： H04J3/0688 , G06F1/04 , G06F1/08 , H04J3/0691 , H04L7/0337
摘要： A clocking mechanism with improved fault tolerance for synchronizing a distributed processing system includes a plurality of distributed clock sources. Each clock source may operate as a master clock for synchronizing the operations of the entire system or as a slave to an external clock while remaining available, in a backup capacity, to operate as a master clock in the event of a failure in the previous master clock. A clock selection mechanism is provided in each distributed switch element for selecting the best clock available to each switch element for synchronization. A failure recovery mechanism is provided with fast and automatic recovery in the event of a failure in a master clock. A data extraction mechanism is also provided capable of sampling a bit stream that is not phase-aligned, even in the presence of timing jitter and pulse width distortion, and having provisions for detecting a bit slip.
摘要翻译：具有改进的用于同步分布式处理系统的容错性的计时机构包括多个分布式时钟源。每个时钟源可以用作主时钟，用于将整个系统的操作或作为从设备的操作同步到外部时钟，同时在备用容量中保持可用，在前一个主站发生故障的情况下作为主时钟操作时钟。在每个分布式开关元件中提供时钟选择机制，用于选择可用于每个开关元件以用于同步的最佳时钟。在主时钟故障的情况下，故障恢复机制提供快速和自动的恢复。即使存在定时抖动和脉冲宽度失真，也提供了能够采样不相位对准的位流的数据提取机构，并且具有用于检测位滑动的规定。

14. 发明授权

US5577075A Distributed clocking system 失效
公开(公告)号：US5577075A
公开(公告)日：1996-11-19
申请号：US766647
申请日：1991-09-26
申请人： John M. Cotton , Nicholas Necula , Bidyut Parruck , Fryderyk Tyra , Alex T. Wissink , Enrique Abreu
发明人： John M. Cotton , Nicholas Necula , Bidyut Parruck , Fryderyk Tyra , Alex T. Wissink , Enrique Abreu
IPC分类号： G06F1/04 , G06F1/08 , H04J3/06 , H04L7/033 , H04L7/00
CPC分类号： H04J3/0688 , G06F1/04 , G06F1/08 , H04J3/0691 , H04L7/0337
摘要： A clocking mechanism with improved fault tolerance for synchronizing a distributed processing system includes a plurality of distributed clock sources. Each clock source may operate as a master clock for synchronizing the operations of the entire system or as a slave to an external clock while remaining available, in a backup capacity, to operate as a master clock in the event of a failure in the previous master clock. A clock selection mechanism is provided in each distributed switch element for selecting the best clock available to each switch element for synchronization. A failure recovery mechanism is provided with fast and automatic recovery in the event of a failure in a master clock. A data extraction mechanism is also provided capable of sampling a bit stream that is not phase-aligned, even in the presence of timing jitter and pulse width distortion, and having provisions for detecting a bit slip.

15. 发明授权

US5142529A Method and means for transferring a data payload from a first SONET signal to a SONET signal of different frequency 失效
标题翻译：用于将数据有效载荷从第一SONET信号传送到不同频率的SONET信号的方法和装置
公开(公告)号：US5142529A
公开(公告)日：1992-08-25
申请号：US559636
申请日：1990-07-27
申请人： Bidyut Parruck , Daniel C. Upp
发明人： Bidyut Parruck , Daniel C. Upp
IPC分类号： G06F5/10 , G06F5/12 , H04J3/06 , H04J3/07 , H04J3/16 , H04L25/05
CPC分类号： G06F5/12 , H04J3/0623 , H04J3/076 , H04J3/1611 , H04L25/05 , G06F2205/123 , Y10S370/907
摘要： An apparatus and method for transferring a data payload (SPE) from a first substantially SONET signal into a second substantially SONET signal of different frequency is provided. The apparatus has: a circuit for extracting the SPE from the first SONET signal and sending the bytes of the SPE, according to a first clock, to a FIFO for storage; a circuit for obtaining the SPE bytes from the FIFO according to a second clock, for building the SPE into the second substantially SONET signal; and a circuit for comparing the relative byte phases of the first and second clocks. The byte phase comparison circuit serves two functions. In order to avoid read/write conflicts in the FIFO, it generates and sends a signal to the extracting circuit which causes the extracting circuit to change the byte phase (i.e. timing) at which bytes are sent to the FIFO. Also, in order to adjust the SPE for frequency differences between the first and second substantially SONET signals, the byte phase comparison circuits sends a signal to the circuit which builds the second substantially SONET signal when the two SONET signals have slipped a byte relative to each other. In response thereto, the second substantially SONET signal building circuit generates a negative or positive stuff.
摘要翻译：提供了一种用于将数据有效载荷（SPE）从第一基本SONET信号传送到不同频率的第二基本SONET信号的装置和方法。该装置具有：用于从第一SONET信号提取SPE并根据第一时钟将SPE的字节发送到FIFO以存储的电路; 用于根据第二时钟从FIFO获取SPE字节的电路，用于将SPE构建成第二基本SONET信号; 以及用于比较第一和第二时钟的相对字节相位的电路。字节相位比较电路有两个功能。为了避免FIFO中的读/写冲突，它产生并发送一个信号到提取电路，使得提取电路将字节发送到FIFO的字节相位（即定时）改变。此外，为了调整第一和第二基本SONET信号之间的频率差的SPE，当两个SONET信号相对于每个SONET信号滑过一个字节时，字节相位比较电路向建立第二基本SONET信号的电路发送信号其他。响应于此，第二基本上SONET信号建立电路产生负的或正的东西。

16. 发明授权

US4799144A Multi-function communication board for expanding the versatility of a computer 失效
标题翻译：多功能通讯板，用于扩展电脑的多功能性
公开(公告)号：US4799144A
公开(公告)日：1989-01-17
申请号：US659989
申请日：1984-10-12
申请人： Bidyut Parruck , Hoshang D. Mulla
发明人： Bidyut Parruck , Hoshang D. Mulla
IPC分类号： G06F3/16 , H04M1/247 , H04M1/27 , H04M1/60 , H04M1/652 , H04M3/00 , H04M3/42 , H04M3/533 , H04M11/06 , H04M19/04
CPC分类号： H04M1/271 , G06F3/16 , H04M1/247 , H04M1/6033 , H04M1/652 , H04M11/06 , H04M19/04 , H04M3/005 , H04M3/42 , H04M3/533 , H04M2250/74 , Y10S379/908
摘要： A single board multiple option card for expanding the versatility of a host computer includes an onboard microprocessor, a digital signal processor and a switched memory device. The switched memory is accessible by the onboard microprocessor and the digital signal processor under the control of the onboard microprocessor. The card further includes an analog signal interface having a plurality of switches, the positions of which are controlled by the onboard microprocessor. As a result, multiple options are provided by varying the positions of the switches. Typically, such options may include: "Invisible Keyboard"; "Voice Command Over Telephone Lines"; "Voice Store and Forward Over the Telephone"; "Voice Record and Playback"; and "Hands-free Telephone".
摘要翻译：用于扩展主计算机的多功能性的单板多选卡包括板载微处理器，数字信号处理器和切换存储器装置。开关存储器可由板载微处理器和数字信号处理器在板载微处理器的控制下访问。该卡还包括具有多个开关的模拟信号接口，其位置由机载微处理器控制。结果，通过改变开关的位置来提供多个选项。通常，这些选项可能包括：“隐形键盘”; “电话线指挥”; “语音存储并通过电话转发”; “录音回放”; 和“免提电话”。

17. 发明授权

US07295574B1 Multi-service segmentation and reassembly device involving multiple data path integrated circuits 有权
标题翻译：多业务分段和重组装置涉及多个数据路径集成电路
公开(公告)号：US07295574B1
公开(公告)日：2007-11-13
申请号：US09976504
申请日：2001-10-12
申请人： Bidyut Parruck , Chulanur Ramakrishnan
发明人： Bidyut Parruck , Chulanur Ramakrishnan
IPC分类号： H04L12/56
CPC分类号： H04L47/621 , H04L12/5601 , H04L12/5602 , H04L47/22 , H04L47/2441 , H04L47/35 , H04L47/50 , H04L49/90 , H04L49/9094 , H04L2012/5652 , H04L2012/5658 , H04L2012/5667 , H04L2012/5669
摘要： A multi-service segmentation and reassembly (MS-SAR) integrated circuit is disposed on a line card in a router or switch. The MS-SAR can operate in an ingress mode so that it receives packet and/or cell format data and forwards that data to either a packet-based or a cell-based switch fabric. The MS-SAR can also operate in an egress mode so that it receives data from either a packet-based or a cell-based switch fabric and outputs that data in packet and/or cell format. The MS-SAR has a data path through which many flows of different traffic types are processed simultaneously. Each flow is processed by functional blocks along the data path in accordance with one of several application types, the application type for a flow being predetermined by the host processor of the router or switch. Segmentation, reassembly and partitioning techniques are disclosed that reduce costs and facilitate high-speed operation.
摘要翻译：在路由器或交换机的线路卡上设置多业务分段和重组（MS-SAR）集成电路。 MS-SAR可以以入口模式操作，以便它接收分组和/或小区格式数据，并将该数据转发到基于分组或基于小区的交换结构。 MS-SAR还可以以出口模式操作，从而从基于分组或基于小区的交换结构接收数据，并以分组和/或小区格式输出该数据。 MS-SAR具有数据路径，同时处理不同流量类型的许多流。根据多个应用类型之一，沿着数据路径的功能块处理每个流程，流程的应用类型由路由器或交换机的主机处理器预先确定。公开了降低成本并促进高速运行的分段，重组和分区技术。

18. 发明授权

US07145910B2 Methods and apparatus for dynamically allocating bandwidth between ATM cells and packets 有权
标题翻译：在ATM信元和数据包之间动态分配带宽的方法和装置
公开(公告)号：US07145910B2
公开(公告)日：2006-12-05
申请号：US10869379
申请日：2004-06-15
申请人： Bidyut Parruck , Joseph A. Nguyen , Chulanur Ramakrishnan
发明人： Bidyut Parruck , Joseph A. Nguyen , Chulanur Ramakrishnan
IPC分类号： H04J3/24 , H04L12/56
CPC分类号： H04L12/5602 , H04J3/1617 , H04J3/1682 , H04J2203/0069 , H04J2203/0089 , H04L12/5601 , H04L2012/5605 , H04L2012/5632 , H04L2012/5652 , H04L2012/5665 , H04L2012/5672
摘要： A method for dynamically allocating bandwidth among ATM cells and packets scheduled for output from an aggregation multiplexer of a transport-layer device configured to multiplex both ATM cells and packets onto the same channel of an optical fiber. The method includes local control and relative priority lookup of incoming ATM cells and packets to support output decision. When compared to currently employed methods, the required level of coordination with the receiving circuit for dynamic bandwidth allocation is substantially lower, thereby reducing operational complexity for network operators and latency for critical data when reallocating bandwidth.
摘要翻译：一种用于动态分配ATM信元之间的带宽和被调度从输出层传输层设备的聚合多路复用器输出的分组的方法，该传输层设备被配置为将ATM信元和分组复用到光纤的同一信道上。该方法包括本地控制和对ATM信元和数据包的相对优先级查询，以支持输出决策。与当前使用的方法相比，用于动态带宽分配的接收电路所需的协调水平显着降低，从而降低网络运营商的运营复杂性，并在重新分配带宽时降低关键数据的延迟。

19. 发明授权

US07139271B1 Using an embedded indication of egress application type to determine which type of egress processing to perform 有权
标题翻译：使用出口应用类型的嵌入式指示来确定要执行哪种类型的出口处理
公开(公告)号：US07139271B1
公开(公告)日：2006-11-21
申请号：US09976499
申请日：2001-10-12
申请人： Bidyut Parruck , Chulanur Ramakrishnan
发明人： Bidyut Parruck , Chulanur Ramakrishnan
IPC分类号： H04L12/54
CPC分类号： H04L47/621 , H04L12/5601 , H04L12/5602 , H04L47/22 , H04L47/2441 , H04L47/35 , H04L47/50 , H04L49/90 , H04L49/9094 , H04L2012/5652 , H04L2012/5658 , H04L2012/5667 , H04L2012/5669
摘要： A multi-service segmentation and reassembly (MS-SAR) integrated circuit is disposed on a line card in a router or switch. The MS-SAR can operate in an ingress mode so that it receives packet and/or cell format data and forwards that data to either a packet-based or a cell-based switch fabric. The MS-SAR can also operate in an egress mode so that it receives data from either a packet-based or a cell-based switch fabric and outputs that data in packet and/or cell format. The MS-SAR has a data path through which many flows of different traffic types are processed simultaneously. Each flow is processed by functional blocks along the data path in accordance with one of several application types, the application type for a flow being predetermined by the host processor of the router or switch. Segmentation, reassembly and partitioning techniques are disclosed that reduce costs and facilitate high-speed operation.
摘要翻译：在路由器或交换机的线路卡上设置多业务分段和重组（MS-SAR）集成电路。 MS-SAR可以以入口模式操作，以便它接收分组和/或小区格式数据，并将该数据转发到基于分组或基于小区的交换结构。 MS-SAR还可以以出口模式操作，从而从基于分组或基于小区的交换结构接收数据，并以分组和/或小区格式输出该数据。 MS-SAR具有数据路径，同时处理不同流量类型的许多流。根据多个应用类型之一，沿着数据路径的功能块处理每个流程，流程的应用类型由路由器或交换机的主机处理器预先确定。公开了降低成本并促进高速运行的分段，重组和分区技术。

20. 发明授权

US07002978B2 Scheduling techniques for data cells in a data switch 失效
标题翻译：数据交换机中数据单元的调度技术
公开(公告)号：US07002978B2
公开(公告)日：2006-02-21
申请号：US09780054
申请日：2001-02-09
申请人： Bidyut Parruck , Chetan V. Sanghvi , Vinay Kumar Bhasin , Makarand Dharmapurikar , Uday Govind Joshi
发明人： Bidyut Parruck , Chetan V. Sanghvi , Vinay Kumar Bhasin , Makarand Dharmapurikar , Uday Govind Joshi
IPC分类号： H04L12/56
CPC分类号： H04L12/5601 , H04L49/106 , H04L49/1553 , H04L49/1576 , H04L2012/5635 , H04L2012/5651 , H04L2012/5679 , H04L2012/5681 , H04L2012/5682 , H04L2012/5683
摘要： A computer-implemented method for scheduling cells output on an output path of a data switch. The data switch is configured for switching the cells from a plurality of input paths to the output path. The method includes providing a plurality of queues, each queue of the plurality of queues having an assigned weight, respective ones of the plurality of input paths being coupled to respective ones of the plurality of queues. The method further includes providing a plurality of queues of queues. The plurality of queues being coupled to the plurality of queues of queues with queues of the plurality of queues having a similar weight being coupled a same queue of queues of the plurality of queues of queues. There is further included providing a scheduler, the plurality of queues of queues being input into the scheduler, the scheduler being coupled to the output path.
摘要翻译：一种用于在数据交换机的输出路径上调度小区输出的计算机实现的方法。数据开关被配置用于将单元从多个输入路径切换到输出路径。所述方法包括提供多个队列，所述多个队列中的每个队列具有分配权重，所述多个输入路径中的相应输入路径被耦合到所述多个队列中的相应队列。该方法还包括提供多个队列队列。多个队列被耦合到队列的多个队列，其中具有相似权重的多个队列的队列被耦合在队列的多个队列的相同队列中。还包括提供调度器，多个队列队列被输入到调度器中，调度器被耦合到输出路径。

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