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11. 发明申请

US20120227026A1 Method and Apparatus for Placement and Routing of Partial Reconfiguration Modules 有权
标题翻译：部分重新配置模块的放置和路由的方法和装置
公开(公告)号：US20120227026A1
公开(公告)日：2012-09-06
申请号：US13040255
申请日：2011-03-03
申请人： David Samuel Goldman , Mark Bourgeault , Vaughn Betz , Alan Louis Herrmann
发明人： David Samuel Goldman , Mark Bourgeault , Vaughn Betz , Alan Louis Herrmann
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5054 , G06F17/5072 , G06F2217/72
摘要： A method for designing a system on a target device includes assigning resources on the target device to static logic modules and partial reconfigurable (PR) modules in the system. The instances of one of the PR modules are placed and routed in parallel utilizing resources from those that are assigned. Other embodiments are also disclosed.
摘要翻译：用于在目标设备上设计系统的方法包括将目标设备上的资源分配给系统中的静态逻辑模块和部分可重新配置（PR）模块。其中一个PR模块的实例使用分配的那些资源进行并行布置和路由。还公开了其他实施例。

12. 发明授权

US08468487B1 Method and apparatus for implementing cross-talk based booster wires in a system on a field programmable gate array 有权
标题翻译：用于在现场可编程门阵列上的系统中实现基于串扰的升压线的方法和装置
公开(公告)号：US08468487B1
公开(公告)日：2013-06-18
申请号：US12386739
申请日：2009-04-22
申请人： Zahir Parpia , Chris Wysocki , Vaughn Betz
发明人： Zahir Parpia , Chris Wysocki , Vaughn Betz
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/5077
摘要： A method for designing a system on a field programmable gate array (FPGA) includes routing one or more booster wires alongside an interconnect to reduce a delay of a signal being transmitted on the interconnect. According to one aspect of the present invention, the routing of the one or more booster wires is performed in response to determining that a timing requirement of the system has not been met.
摘要翻译：用于在现场可编程门阵列（FPGA）上设计系统的方法包括在互连旁边布置一个或多个升压线，以减少在互连上传输的信号的延迟。根据本发明的一个方面，响应于确定尚未满足系统的定时要求，执行一个或多个升压线的路由。

13. 发明授权

US08248110B1 Clock switch-over circuits and methods 有权
标题翻译：时钟切换电路和方法
公开(公告)号：US08248110B1
公开(公告)日：2012-08-21
申请号：US13048241
申请日：2011-03-15
申请人： Gary Lai , Andy L. Lee , Ryan Fung , Vaughn Betz , Marcel A. LeBlanc
发明人： Gary Lai , Andy L. Lee , Ryan Fung , Vaughn Betz , Marcel A. LeBlanc
IPC分类号： H01H71/22
CPC分类号： G06F1/10
摘要： Clock switch-over circuits and methods provide clock signals to clock routing networks. According to one embodiment, a multiplexer selects between a first clock signal and a second clock signal in response to a switch select signal received from a control circuit. A storage circuit stores an enable signal in response to an output clock signal of the multiplexer. A logic circuit transmits the output clock signal of the multiplexer to a clock routing network in response to the enable signal from the storage circuit. At least one signal is transmitted from the clock switch-over circuit to the control circuit.
摘要翻译：时钟切换电路和方法为时钟路由网络提供时钟信号。根据一个实施例，多路复用器响应于从控制电路接收的开关选择信号在第一时钟信号和第二时钟信号之间进行选择。存储电路响应于多路复用器的输出时钟信号而存储使能信号。响应于来自存储电路的使能信号，逻辑电路将多路复用器的输出时钟信号传输到时钟路由网络。至少一个信号从时钟切换电路发送到控制电路。

14. 发明授权

US07659764B2 Efficient delay elements 有权
标题翻译：高效延时元件
公开(公告)号：US07659764B2
公开(公告)日：2010-02-09
申请号：US12212314
申请日：2008-09-17
申请人： Ryan Fung , Vaughn Betz
发明人： Ryan Fung , Vaughn Betz
IPC分类号： H03K3/00
CPC分类号： H03K19/17736 , H03K5/133 , H03K19/1778 , H03K19/17792 , H03K2005/00058 , H03K2005/00234
摘要： Circuits, methods, and apparatus for delaying signals in a power and area efficient manner are provided. A gating element within a stage of a programmable delay element suppresses an operation of other stages of the delay element. A programmable delay has components with differing delays that may be combined to give flexibility in choices for delay increments while minimizing the area of the delay element. A delay element is shared between different signal paths, for example, to reduce the number of delay elements or to allow utilizing unused delay elements of other signal paths.
摘要翻译：提供了用于以功率和区域有效的方式延迟信号的电路，方法和装置。可编程延迟元件的级内的门控元件抑制延迟元件的其他级的操作。可编程延迟具有不同延迟的组件，其可以组合以在延迟增量的选择中提供灵活性，同时最小化延迟元件的面积。延迟元件在不同的信号路径之间被共享，例如，以减少延迟元件的数量或允许利用其他信号路径的未使用的延迟元件。

15. 发明授权

US07656191B2 Distributed memory in field-programmable gate array integrated circuit devices 有权
标题翻译：现场可编程门阵列集成电路器件中的分布式存储器
公开(公告)号：US07656191B2
公开(公告)日：2010-02-02
申请号：US12156403
申请日：2008-05-30
申请人： David Lewis , Paul Leventis , Vaughn Betz , Thomas Yau-Tsun Wong , Andy Lee , Philip Pan
发明人： David Lewis , Paul Leventis , Vaughn Betz , Thomas Yau-Tsun Wong , Andy Lee , Philip Pan
IPC分类号： H03K19/177
CPC分类号： G11C7/1045 , H03K19/17728 , H03K19/17736 , H03K19/1776
摘要： Circuitry for facilitating the use of the memory elements in the look-up tables (“LUTs”) of a field programmable gate array (“FPGA”) as user-accessible, distributed RAM. For example, a register associated with a LUT and that is not needed in the read data path in user RAM mode can be used to register data for writing in user RAM mode. As another example, an otherwise unneeded register associated with a LUT can be used to provide a synchronous read address signal for user RAM mode. Several other features are shown for similarly facilitating user RAM mode with minimal (if any) additional circuitry being required in the FPGA.
摘要翻译：用于便于将现场可编程门阵列（“FPGA”）的查找表（“LUT”）中的存储元件用作用户可访问的分布式RAM的电路。例如，可以使用与用户RAM模式中的与LUT相关联并且在读取数据路径中不需要的寄存器来登记用于用户RAM模式的写入数据。作为另一示例，可以使用与LUT相关联的另外不需要的寄存器来提供用于用户RAM模式的同步读取地址信号。显示了几个其他功能，用于在FPGA中需要最少（如果有的话）附加电路的同时方便用户RAM模式。

16. 发明授权

US07555741B1 Computer-aided-design tools for reducing power consumption in programmable logic devices 有权
标题翻译：用于降低可编程逻辑器件功耗的计算机辅助设计工具
公开(公告)号：US07555741B1
公开(公告)日：2009-06-30
申请号：US11520944
申请日：2006-09-13
申请人： David Ian M. Milton , David Neto , Vaughn Betz
发明人： David Ian M. Milton , David Neto , Vaughn Betz
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F2217/78
摘要： Methods and apparatus for designing and producing programmable logic devices are provided. A logic design system may be used to analyze various implementations of a desired logic design for a programmable logic device integrated circuit. The logic design system may be used to produce configuration data for the programmable logic device in accordance with an implementation that minimizes power consumption by the programmable logic device. The programmable logic device contains logic blocks that are used to implement the desired logic design and logic blocks that are unused. Dynamic power consumption can be minimized by identifying which configuration data settings reduce the amount of signal toggling in the unused logic blocks and routing, and by minimizing the capacitance of resources that do toggle. Clock tree power consumption can be reduced by evaluating multiple potential logic design implementations using a strictly concave cost function.
摘要翻译：提供了设计和制造可编程逻辑器件的方法和设备。可以使用逻辑设计系统来分析用于可编程逻辑器件集成电路的期望逻辑设计的各种实现。逻辑设计系统可以用于根据使可编程逻辑器件的功耗最小化的实现来产生可编程逻辑器件的配置数据。可编程逻辑器件包含用于实现未使用的所需逻辑设计和逻辑块的逻辑块。可以通过识别哪些配置数据设置减少未使用的逻辑块和路由中的信号切换量以及通过最小化切换的资源的电容来最小化动态功耗。通过使用严格的凹成本函数评估多个潜在的逻辑设计实现，可以减少时钟树的功耗。

17. 发明申请

US20080263481A1 APPARATUS AND METHODS FOR POWER MANAGEMENT IN INTEGRATED CIRCUITS 有权
标题翻译：集成电路中电源管理的装置和方法
公开(公告)号：US20080263481A1
公开(公告)日：2008-10-23
申请号：US12165665
申请日：2008-07-01
申请人： David Lewis , Christopher F. Lane , Sarathy Sribhashyam , Srinivas Perisetty , Tim Vanderhoek , Vaughn Betz , Thomas Yau-Tsun Wong , Andy L. Lee
发明人： David Lewis , Christopher F. Lane , Sarathy Sribhashyam , Srinivas Perisetty , Tim Vanderhoek , Vaughn Betz , Thomas Yau-Tsun Wong , Andy L. Lee
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5077 , H03K19/17784
摘要： A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.
摘要翻译：可编程逻辑器件（PLD）包括非易失性存储器，配置存储器和控制电路。控制电路耦合到非易失性存储器和配置存储器。一组电压从控制电路的输出导出，并被应用于PLD内的电路。

18. 发明申请

US20080231316A1 Distributed memory in field-programmable gate array integrated circuit devices 有权
标题翻译：现场可编程门阵列集成电路器件中的分布式存储器
公开(公告)号：US20080231316A1
公开(公告)日：2008-09-25
申请号：US12156403
申请日：2008-05-30
申请人： David Lewis , Paul Leventis , Vaughn Betz , Thomas Yau-Tsun Wong , Andy Lee , Philip Pan
发明人： David Lewis , Paul Leventis , Vaughn Betz , Thomas Yau-Tsun Wong , Andy Lee , Philip Pan
IPC分类号： H03K19/177
CPC分类号： G11C7/1045 , H03K19/17728 , H03K19/17736 , H03K19/1776
摘要： Circuitry for facilitating the use of the memory elements in the look-up tables (“LUTs”) of a field programmable gate array (“FPGA”) as user-accessible, distributed RAM. For example, a register associated with a LUT and that is not needed in the read data path in user RAM mode can be used to register data for writing in user RAM mode. As another example, an otherwise unneeded register associated with a LUT can be used to provide a synchronous read address signal for user RAM mode. Several other features are shown for similarly facilitating user RAM mode with minimal (if any) additional circuitry being required in the FPGA.
摘要翻译：用于便于将现场可编程门阵列（“FPGA”）的查找表（“LUT”）中的存储元件用作用户可访问的分布式RAM的电路。例如，可以使用与用户RAM模式中的与LUT相关联并且在读取数据路径中不需要的寄存器来登记用于用户RAM模式的写入数据。作为另一示例，可以使用与LUT相关联的另外不需要的寄存器来提供用于用户RAM模式的同步读取地址信号。显示了几个其他功能，用于在FPGA中需要最少（如果有的话）附加电路的同时方便用户RAM模式。

19. 发明授权

US07400167B2 Apparatus and methods for optimizing the performance of programmable logic devices 有权
标题翻译：用于优化可编程逻辑器件性能的装置和方法
公开(公告)号：US07400167B2
公开(公告)日：2008-07-15
申请号：US11204570
申请日：2005-08-16
申请人： David Lewis , Vaughn Betz , Paul Leventis , Christopher Lane , Andy Lee , Jeffrey Watt , Timothy Vanderhoek
发明人： David Lewis , Vaughn Betz , Paul Leventis , Christopher Lane , Andy Lee , Jeffrey Watt , Timothy Vanderhoek
IPC分类号： H03K19/173
CPC分类号： G06F17/5081 , G06F17/5077 , H03K19/17784
摘要： A programmable logic device (PLD) includes first and second circuits. The first and second circuits are part of a user's design to be implemented using the PLD's resources. The first circuit is powered by a first supply voltage. The second circuit is powered by a second supply voltage. At least one of the first and second supply voltages is determined by a PLD computer-aided design (CAD) flow used to implement the user's design in the PLD.
摘要翻译：可编程逻辑器件（PLD）包括第一和第二电路。第一和第二电路是使用PLD资源实现的用户设计的一部分。第一个电路由第一个电源供电。第二电路由第二电源供电。第一和第二电源电压中的至少一个由用于在PLD中实现用户设计的PLD计算机辅助设计（CAD）流确定。

20. 发明授权

US07397726B1 Flexible RAM clock enable 失效
标题翻译：灵活的RAM时钟使能
公开(公告)号：US07397726B1
公开(公告)日：2008-07-08
申请号：US11399771
申请日：2006-04-07
申请人： Jinyong Yuan , Christopher F. Lane , David E. Jefferson , Vaughn Betz
发明人： Jinyong Yuan , Christopher F. Lane , David E. Jefferson , Vaughn Betz
IPC分类号： G11C8/00 , G11C7/10
CPC分类号： G11C7/1075 , G11C8/18 , H03K19/1737
摘要： A first set of configuration logic is configurable to provide a first port input clock signal for controlling input registers of a first port of a memory block. The first set of configuration logic is also configurable to provide a first port core clock signal for controlling the memory block core. The first port core clock signal can either be the same as the first port input clock signal, or can be controlled independently from the first port input clock signal. A second set of configuration logic is configurable to provide a second port input clock signal for controlling input registers of a second port of the memory block. The second set of configuration logic is also configurable to provide a second port core clock signal for controlling the memory block core. The second port core clock signal can be controlled independently from the second port input clock signal.
摘要翻译：第一组配置逻辑可配置为提供用于控制存储器块的第一端口的输入寄存器的第一端口输入时钟信号。第一组配置逻辑也可配置为提供用于控制存储块核心的第一端口核心时钟信号。第一个端口核心时钟信号可以与第一个端口输入时钟信号相同，也可以独立于第一个端口输入时钟信号进行控制。第二组配置逻辑可配置为提供用于控制存储器块的第二端口的输入寄存器的第二端口输入时钟信号。第二组配置逻辑也可配置为提供用于控制存储块核心的第二端口核心时钟信号。可以独立于第二端口输入时钟信号来控制第二端口核心时钟信号。

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