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11. 发明授权

US07474153B1 Dual stage source/sink amplifier circuit with quiescent current determination 有权
标题翻译：具有静态电流确定的双级源极/漏极放大器电路
公开(公告)号：US07474153B1
公开(公告)日：2009-01-06
申请号：US11789170
申请日：2007-04-24
申请人： Uday Dasgupta
发明人： Uday Dasgupta
IPC分类号： H03F3/45
CPC分类号： H03F3/45475 , H03F3/3022 , H03F2200/78 , H03F2203/45138 , H03F2203/45244 , H03F2203/45536
摘要： An amplifier circuit includes a first stage that receives a signal input and a control input and that generates first stage outputs. A second stage that communicates with the first stage and the control input and that includes a current source drivers. Each of the current source drivers have a constant current source mode and a driver mode. The constant current source mode and the driver mode are selected based on the signal input and the control input. A comparator circuit compares current through the current source drivers with a reference current. A control circuit generates the control input based on the comparison.
摘要翻译：放大器电路包括接收信号输入和控制输入并且产生第一级输出的第一级。与第一阶段和控制输入通信的第二阶段，其包括当前的源驱动器。每个电流源驱动器具有恒流源模式和驱动模式。根据信号输入和控制输入选择恒流源模式和驱动模式。比较器电路将电流源驱动器与参考电流进行比较。控制电路根据比较生成控制输入。

12. 发明授权

US06727768B1 Relaxation CCO for PLL-based constant tuning of GM-C filters 失效
标题翻译：放松CCO用于基于PLL的时间常数调整GM-C滤波器
公开(公告)号：US06727768B1
公开(公告)日：2004-04-27
申请号：US10282889
申请日：2002-10-29
申请人： Uday Dasgupta
发明人： Uday Dasgupta
IPC分类号： H03B524
CPC分类号： H03K3/0231
摘要： A relaxation current controlled oscillator (CCO) is provided by forming an integrator out of a transconductance amplifier and a capacitor. The output of the integrator is fed to comparators which in turn feed a bistable circuit. The outputs of the bistable circuit control either the polarity of the input signals to the transconductance amplifier or the polarity of the input signals to the comparators. Switches, controlled by the bistable circuit, in turn control the polarity of the input signals. The feedback path created by the transconductance amplifier, comparators, flip-flops, and switches produces continuous oscillations. A DC current input adjusts the gm of the transconductance amplifier allowing the oscillation frequency of the CCO to be adjusted. Several embodiments of CCOs are described which are fully compatible with PLLs with automatic time-constant or bandwidth tuning of a gm-C filter.
摘要翻译：通过从跨导放大器和电容器形成积分器来提供弛豫电流控制振荡器（CCO）。积分器的输出馈送到比较器，反馈器又馈送双稳态电路。双稳态电路的输出将输入信号的极性控制到跨导放大器，或将输入信号的极性控制到比较器。由双稳态电路控制的开关又控制输入信号的极性。由跨导放大器，比较器，触发器和开关产生的反馈路径产生连续振荡。 DC电流输入调节跨导放大器的gm，允许调整CCO的振荡频率。描述了CCO的几个实施例，其与具有gm-C滤波器的自动时间常数或带宽调谐的PLL完全兼容。

13. 发明授权

US06545502B1 High frequency MOS fixed and variable gain amplifiers 失效
标题翻译：高频MOS固定和可变增益放大器
公开(公告)号：US06545502B1
公开(公告)日：2003-04-08
申请号：US10036597
申请日：2001-11-09
申请人： Uday Dasgupta , Wooi Gan Yeoh
发明人： Uday Dasgupta , Wooi Gan Yeoh
IPC分类号： H03K1716
CPC分类号： H03F3/45089 , H03F3/45188 , H03F3/45197 , H03F2203/45311 , H03F2203/45526 , H03F2203/45574 , H03F2203/45702 , H03G1/0023
摘要： A high frequency differential amplifier with a circuit topology which ensures that bias currents of the high transconductance differential transistors with minimum channel length are exactly equal, i.e., each differential transistor carries exactly half of the total current I0 of the differential amplifier. This is achieved by coupling each differential transistor via its own current source to the reference potential. To insure a good match between the current sources, the current source devices are made with long channel lengths. Impedances are coupled between the junctions of each differential transistor pair and its current source to insure good AC gain. For the variable gain differential amplifier the spread in the gain control characteristics is reduced by making the aspect ratio of the first pair of differential transistors larger than that of the second pair of differential transistors.
摘要翻译：具有电路拓扑的高频差分放大器，其确保具有最小沟道长度的高跨导差分晶体管的偏置电流精确相等，即，每个差分晶体管正好携带差分放大器的总电流I0的一半。这通过将每个差分晶体管经由其自身的电流源耦合到参考电位来实现。为了确保电流源之间的良好匹配，当前的源器件长沟道长度制成。阻抗耦合在每个差分晶体管对与其电流源的结之间，以确保良好的交流增益。对于可变增益差分放大器，通过使第一对差分晶体管的纵横比大于第二对差分晶体管的宽高比来减小增益控制特性中的扩展。

14. 发明授权

US06529077B1 Gain compensation circuit for CMOS amplifiers 失效
标题翻译： CMOS放大器的增益补偿电路
公开(公告)号：US06529077B1
公开(公告)日：2003-03-04
申请号：US09933964
申请日：2001-08-22
申请人： Uday Dasgupta
发明人： Uday Dasgupta
IPC分类号： H03F345
CPC分类号： H03F1/306 , H03F2203/45024 , H03F2203/45456 , H03F2203/45466 , H03F2203/45476
摘要： A gain compensation circuit that compensates for variations in gain of a high gain, high frequency amplifier due to changes in mobility of transistor and resistor components of the amplifier. The gain compensation circuit includes a current adjustment circuit and a gain factor evaluation circuit. The current adjustment circuit modifies a bias current provided to each amplifier stage of a plurality of amplifier stages that make up the high gain, high frequency amplifier. The modification of the bias current adjusts the gain factor of the amplifier. The gain factor evaluation circuit is in communication with the current adjustment circuit to determine changes in the gain factor of the high gain, high frequency amplifier. From the determination, the gain factor evaluation circuit provides a compensation signal to the current adjustment circuit indicating a modification factor for the biasing current for each amplifier stage.
摘要翻译：一种增益补偿电路，其补偿由于放大器的晶体管和电阻器组件的迁移率的变化引起的高增益高频放大器的增益变化。增益补偿电路包括电流调节电路和增益因子评估电路。电流调节电路修改提供给组成高增益高频放大器的多个放大器级的每个放大级的偏置电流。偏置电流的修改调整放大器的增益系数。增益因子评估电路与电流调节电路通信，以确定高增益高频放大器的增益因子的变化。从该确定，增益因子评估电路向当前调整电路提供指示每个放大器级的偏置电流的修正系数的补偿信号。

15. 发明授权

US6144238A Integrated power-on-reset circuit 有权
标题翻译：集成上电复位电路
公开(公告)号：US6144238A
公开(公告)日：2000-11-07
申请号：US151156
申请日：1998-09-10
申请人： Uday Dasgupta
发明人： Uday Dasgupta
IPC分类号： H03K3/3565 , H03K17/22 , H03L7/00
CPC分类号： H03K17/223 , H03K3/3565
摘要： A circuit and a method are disclosed which offer a solution for integrating a power-on-reset circuit that is realizable in a small space, consumes very little power, and works for practically any rate of rise of the power supply. These goals have been achieved by detecting, in a first section of the circuit, when the supply voltage reaches the threshold voltage V.sub.TP of a p-channel transistor, and activates power-on-reset by forcing that signal to logical zero (active). This first section detects next when the supply voltage reaches 2V.sub.TP and signals to a second section of the circuit to start charging a capacitor. The charging rate of the capacitor is controlled in such a way that its voltage lags behind the supply voltage, so that if the rise of the supply voltage is very fast, the duration T.sub.D of power-on-reset is long enough to insure complete resetting of the circuits it serves, such as digital memory elements, digital registers etc. A third section of the circuit monitors the voltage of the capacitor and when this capacitor voltage has reached a certain predetermined percentage of the supply voltage, this third section terminates power-on-reset by switching that signal to logical one (inactive).
摘要翻译：公开了一种电路和方法，其提供用于集成可在小空间中实现的上电复位电路的解决方案，消耗很少的功率，并且几乎可用于电源的上升速率。这些目标已经通过在电路的第一部分中检测到当电源电压达到p沟道晶体管的阈值电压VTP并且通过将该信号强制为逻辑零（激活）而激活上电复位来实现。此第一部分检测电源电压达到2VTP时的信号，并向电路的第二部分发送信号，开始对电容充电。电容器的充电速率被控制为使其电压落在电源电压之后，因此如果电源电压的上升非常快，则上电复位的持续时间TD足够长以确保完全复位例如数字存储器元件，数字寄存器等。电路的第三部分监视电容器的电压，并且当该电容器电压达到电源电压的一定预定百分比时，该第三部分终止电源 - 通过将该信号切换到逻辑1（无效）来进行复位。

16. 发明授权

US6085327A Area-efficient integrated self-timing power start-up reset circuit with delay of the start-up reset until the system clock is stabilized 失效
标题翻译：具有区域效能的集成自定时功率启动复位电路，具有启动复位延时，直到系统时钟稳定
公开(公告)号：US6085327A
公开(公告)日：2000-07-04
申请号：US58124
申请日：1998-04-10
申请人： Yap Hwa Seng , Uday Dasgupta , Chan Chee Oei
发明人： Yap Hwa Seng , Uday Dasgupta , Chan Chee Oei
IPC分类号： G06F1/24 , H03K17/22 , G06F1/26
CPC分类号： H03K17/223 , G06F1/24
摘要： A circuit and a method are disclosed for a power start-up reset circuit which is self-timing and which can be fully integrated in a standard CMOS or BiCMOS process along with other digital circuits. The circuit provides a system reset signal which is issued only after all circuit have stabilized by making the issuance of this system reset signal dependent on an oscillator becoming stable and a subsequent count of a fixed number of system clock cycles derived from that oscillator.
摘要翻译：公开了一种用于启动复位电路的电路和方法，该电路是自定时的，并且可以与其他数字电路一起完全集成在标准CMOS或BiCMOS工艺中。该电路提供系统复位信号，该信号仅在所有电路通过使振荡器变得稳定的依赖于该系统复位信号的发出以及由该振荡器导出的固定数量的系统时钟周期的后续计数之后才发出。

17. 发明授权

US6052011A Fractional period delay circuit 失效
标题翻译：分数周期延迟电路
公开(公告)号：US6052011A
公开(公告)日：2000-04-18
申请号：US966736
申请日：1997-11-10
申请人： Uday Dasgupta
发明人： Uday Dasgupta
IPC分类号： H03H11/26 , H03L7/07 , H03L7/081 , H03L7/093
CPC分类号： H03L7/0812 , H03H11/265 , H03L7/07 , H03L7/093
摘要： A fractional period delay circuit to delay a clocking signal by a non-integer fraction of the period of the clocking signal is disclosed. The fractional period delay circuit has a first delay line connected to a master timing signal to delay the master clock to form the first timing signal. The fractional period delay circuit has plurality of adjustable delay lines. Each adjustable delay line is connected to the master timing signal to delay the master timing A delay adjustment input will modify the delay of the adjustable delay circuit. The fractional period delay circuit further has a plurality of phase difference detectors connected to the output of the first delay line and to the output of one of the plurality of adjustable delay lines. The phase difference detector will create a difference signal indicating a difference in phase between the first timing signal and one of the delayed timing signals. A plurality of sequence timing signals are created in a is timing sequence generator. A phase correction calculators is connected to a phase difference detector and the timing sequence generator to calculate a delay adjustment signal. The delay adjustment signal is an error signal indicating the delay between the delayed timing signal and the first timing signal. The delay adjustment signal is transferred to a delay line adjustment circuit to adjust the delay of the adjustable delay line.
摘要翻译：公开了一种将时钟信号延迟时钟信号周期的非整数分数的分数周期延迟电路。分数周期延迟电路具有连接到主定时信号的第一延迟线，以延迟主时钟以形成第一定时信号。分数周期延迟电路具有多个可调延迟线。每个可调延迟线连接到主定时信号以延迟主机定时A延迟调整输入将修改可调延迟电路的延迟。分数周期延迟电路还具有连接到第一延迟线的输出和多个可调延迟线中的一个的输出的多个相位差检测器。相位差检测器将产生指示第一定时信号和延迟定时信号之一的相位差的差分信号。在一个定时序列发生器中产生多个序列定时信号。相位校正计算器连接到相位差检测器和定时序列发生器以计算延迟调整信号。延迟调整信号是指示延迟定时信号和第一定时信号之间的延迟的误差信号。延迟调整信号被传送到延迟线调整电路，以调整可调延迟线的延迟。

18. 发明授权

US5771286A Speech amplifier associated with an LED 失效
标题翻译：与LED相关的语音放大器
公开(公告)号：US5771286A
公开(公告)日：1998-06-23
申请号：US521017
申请日：1995-08-30
申请人： Uday Dasgupta
发明人： Uday Dasgupta
IPC分类号： H04M1/60 , H04M1/76 , H04M1/22
CPC分类号： H04M1/6025 , H04M1/76
摘要： A transmit amplifier for a telephone set without its own power supply has an LED with an anode connected to a first positive terminal of the telephone line and a circuit that determines the ratio between the line current and the line voltage. The LED is supplied with a constant current and this current is derived when the voltage across the terminals of the line becomes lower than a predetermined value.
摘要翻译：用于没有其自身电源的电话机的发射放大器具有连接到电话线的第一正极端子的阳极和确定线路电流与线路电压之间的比率的电路的LED。 LED被提供恒定电流，并且当线路两端的电压变得低于预定值时，导出该电流。

19. 发明授权

US07786804B2 Driving amplifier circuit with digital control and DC offset equalization 有权
标题翻译：具有数字控制和直流偏移均衡的驱动放大器电路
公开(公告)号：US07786804B2
公开(公告)日：2010-08-31
申请号：US12606194
申请日：2009-10-27
申请人： Uday Dasgupta
发明人： Uday Dasgupta
IPC分类号： H03F3/26
CPC分类号： H03F3/45475 , H03F3/45901 , H03F2203/45212 , H03F2203/45216 , H03F2203/45222 , H03F2203/45512 , H03F2203/45644 , H03F2203/45646 , H03F2203/45724
摘要： A driving amplifier circuit includes: a first driver for sourcing a load current to a load; a second driver for sinking the load current from the load; a first operational amplifier (op-amp) for driving the first driver; a second operational amplifier for driving the second driver; a first bias circuit for biasing the first driver; a second bias circuit for biasing the second driver; an enabling circuit for enabling either the first bias circuit or the second bias circuit according to a control signal; a digital control circuit for monitoring currents of the first driver and the second driver to generate the control signal; and an offset equalization circuit, coupled between an internal node of the first operational amplifier and an internal node of the second operational amplifier, for adjusting DC offset of at least one of the first operational amplifier and the second operational amplifier.
摘要翻译：驱动放大器电路包括：用于向负载提供负载电流的第一驱动器; 用于从负载中吸收负载电流的第二个驱动器; 用于驱动第一驱动器的第一运算放大器（运算放大器）; 用于驱动第二驱动器的第二运算放大器; 用于偏置第一驱动器的第一偏置电路; 用于偏置所述第二驱动器的第二偏置电路; 使能电路，用于根据控制信号启动第一偏置电路或第二偏置电路; 数字控制电路，用于监视第一驱动器和第二驱动器的电流以产生控制信号; 以及偏移均衡电路，耦合在所述第一运算放大器的内部节点和所述第二运算放大器的内部节点之间，用于调整所述第一运算放大器和所述第二运算放大器中的至少一个的DC偏移。

20. 发明授权

US07764122B1 Dual stage source/sink amplifier circuit with quiescent current determination 有权
标题翻译：具有静态电流确定的双级源极/漏极放大器电路
公开(公告)号：US07764122B1
公开(公告)日：2010-07-27
申请号：US12337955
申请日：2008-12-18
申请人： Uday Dasgupta
发明人： Uday Dasgupta
IPC分类号： H03F3/45
CPC分类号： H03F3/45475 , H03F3/3022 , H03F2200/78 , H03F2203/45138 , H03F2203/45244 , H03F2203/45536
摘要： An amplifier circuit includes a first stage to generate a first stage output based on a signal input and a control input. A second stage in communication with the first stage output and the control input. The second stage includes a first current source driver operable in a constant current source mode or a driver mode. The first current source driver operates in either the constant current source mode or the driver mode based on the signal input and the control input.
摘要翻译：放大器电路包括基于信号输入和控制输入产生第一级输出的第一级。与第一阶段输出和控制输入通信的第二阶段。第二级包括可在恒流源模式或驱动器模式下操作的第一电流源驱动器。第一个电流源驱动器基于信号输入和控制输入在恒流源模式或驱动模式下工作。

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