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11. 发明授权

US07015129B2 Bond pad scheme for Cu process 失效
标题翻译： Cu工艺的焊盘方案
公开(公告)号：US07015129B2
公开(公告)日：2006-03-21
申请号：US10999464
申请日：2004-11-29
申请人： Chia-Hung Lai , Jiunn-Jyi Lin , Tzong-Sheng Chang , Min Cao , Huan-Chi Tseng , Yu-Hua Lee , Chin-Tien Yang
发明人： Chia-Hung Lai , Jiunn-Jyi Lin , Tzong-Sheng Chang , Min Cao , Huan-Chi Tseng , Yu-Hua Lee , Chin-Tien Yang
IPC分类号： H01L21/44
CPC分类号： H01L24/13 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/0401 , H01L2224/05006 , H01L2224/05624 , H01L2224/05647 , H01L2224/13007 , H01L2224/13099 , H01L2924/0001 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01073 , H01L2924/01082 , H01L2924/01083 , H01L2924/04953 , H01L2924/10329 , H01L2924/14 , H01L2924/19041 , H01L2924/19043
摘要： A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads during subsequent wire bonding processes or flip-chip packaging processes.
摘要翻译：一种形成半导体器件的接合焊盘和新的接合焊盘结构的新颖方法。两个钝化层用于形成半导体器件的接合焊盘。第二钝化层的一部分位于相邻的接合焊盘之间，防止在随后的引线接合过程或倒装芯片封装工艺期间接合焊盘短路。

12. 发明申请

US20050095836A1 Bond pad scheme for Cu process 失效
标题翻译： Cu工艺的焊盘方案
公开(公告)号：US20050095836A1
公开(公告)日：2005-05-05
申请号：US10999464
申请日：2004-11-29
申请人： Chia-Hung Lai , Jiunn-Jyi Lin , Tzong-Sheng Chang , Min Cao , Huan-Chi Tseng , Yu-Hua Lee , Chin-Tien Yang
发明人： Chia-Hung Lai , Jiunn-Jyi Lin , Tzong-Sheng Chang , Min Cao , Huan-Chi Tseng , Yu-Hua Lee , Chin-Tien Yang
IPC分类号： H01L21/28 , H01L21/44 , H01L21/60 , H01L21/768 , H01L23/48 , H01L23/485 , H01L23/52 , H01L29/40
CPC分类号： H01L24/13 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/0401 , H01L2224/05006 , H01L2224/05624 , H01L2224/05647 , H01L2224/13007 , H01L2224/13099 , H01L2924/0001 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01073 , H01L2924/01082 , H01L2924/01083 , H01L2924/04953 , H01L2924/10329 , H01L2924/14 , H01L2924/19041 , H01L2924/19043
摘要： A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads during subsequent wire bonding processes or flip-chip packaging processes.
摘要翻译：一种形成半导体器件的接合焊盘和新的接合焊盘结构的新颖方法。两个钝化层用于形成半导体器件的接合焊盘。第二钝化层的一部分位于相邻的接合焊盘之间，防止在随后的引线接合过程或倒装芯片封装工艺期间接合焊盘短路。

13. 发明申请

US20060205232A1 Film treatment method preventing blocked etch of low-K dielectrics 审中-公开
标题翻译：防止低K电介质的阻挡蚀刻的膜处理方法
公开(公告)号：US20060205232A1
公开(公告)日：2006-09-14
申请号：US11076702
申请日：2005-03-10
申请人： Lih-Ping Li , Tzong-Sheng Chang , William Kuo , Tsung-Hsien Lee , Chun-Lin Tsai , Szu-An Wu , Yin-Ping Lee
发明人： Lih-Ping Li , Tzong-Sheng Chang , William Kuo , Tsung-Hsien Lee , Chun-Lin Tsai , Szu-An Wu , Yin-Ping Lee
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/0276 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/76802 , H01L21/76825 , H01L21/76826 , H01L21/76828
摘要： A method for etching a dielectric material in a semiconductor device is disclosed. After providing a conductive region, a dielectric layer is formed over the conductive region. A dielectric antireflective coating (DARC) layer is further formed on the dielectric layer. Then, a moisture-removal step is performed that removes moisture from the DARC layer and from an interface region between the dielectric and the DARC layer. A masking pattern is transferred into the DARC layer and the dielectric layer.
摘要翻译：公开了一种在半导体器件中蚀刻介电材料的方法。在提供导电区域之后，在导电区域上形成电介质层。在电介质层上进一步形成电介质抗反射涂层（DARC）层。然后，进行除湿步骤，其从DARC层和电介质层与DARC层之间的界面区域去除水分。掩模图案被传送到DARC层和电介质层。

14. 发明授权

US6004829A Method of increasing end point detection capability of reactive ion etching by adding pad area 失效
标题翻译：通过添加焊盘面积增加反应离子蚀刻终点检测能力的方法
公开(公告)号：US6004829A
公开(公告)日：1999-12-21
申请号：US928229
申请日：1997-09-12
申请人： Tzong-Sheng Chang , Yen-Shih Ho , Ruey-Hsin Liou , Yuan-Cheng Yu
发明人： Tzong-Sheng Chang , Yen-Shih Ho , Ruey-Hsin Liou , Yuan-Cheng Yu
IPC分类号： H01L21/311 , H01L21/66 , H01L21/8247 , H01L23/544 , H01L21/8238
CPC分类号： H01L27/11526 , H01L21/31116 , H01L22/26 , H01L22/34 , H01L27/11539 , H01L2924/0002
摘要： A method of forming a semiconductor device includes forming of layers of polysilicon and dielectric layers in manufacturing a semiconductor device and patterning the layers into devices using phototlithography and etching process steps. End point mode detection is used in the etching process in a way in which the area exposed during etching is increased to enhance the end point detection capacity, by adding a surplus pad area before pad formation. Specifically an EPROM device is formed with a first level of polysilicon above a gate oxide layer patterned into a floating gate electrode of an EPROM device. Then form an ONO layer above the floating gate electrode. Define array protection, grow a second gate oxide layer, deposit a second level of polysilicon, define peripheral gates from the second level of polysilicon, and define an EPROM transistor gate electrode from the second level of polysilicon.
摘要翻译：形成半导体器件的方法包括在制造半导体器件中形成多晶硅层和电介质层，并使用光刻和蚀刻工艺步骤将层图案化成器件。在蚀刻工艺中使用端点模式检测，其中通过在焊盘形成之前添加剩余焊盘区域，在蚀刻期间暴露的区域增加以增强端点检测能力的方式。具体地说，EPROM器件形成有图案化为EPROM器件的浮置栅电极的栅极氧化物层上方的第一级多晶硅。然后在浮栅电极上形成ONO层。定义阵列保护，生长第二栅极氧化层，沉积第二级多晶硅，从第二级多晶硅定义外围栅极，并从第二级多晶硅定义EPROM晶体管栅电极。

15. 发明授权

US06191018B1 Method for selective resistivity adjustment of polycide lines for enhanced design flexibility and improved space utilization in sub-micron integrated circuits 有权
标题翻译：用于增强设计灵活性和改进亚微米集成电路空间利用率的多选线电阻率选择性电阻率调整方法
公开(公告)号：US06191018B1
公开(公告)日：2001-02-20
申请号：US09224716
申请日：1999-01-04
申请人： Wen-Jye Yue , Hsun-Chih Tsao , Tzong-Sheng Chang
发明人： Wen-Jye Yue , Hsun-Chih Tsao , Tzong-Sheng Chang
IPC分类号： H01L214763
CPC分类号： H01L28/20 , H01L27/0629
摘要： A method for forming a polycide layer wherein the silicide layer is blanket deposited over a polysilicon layer and selectively ion implanted through a mask to form regions of a higher resistivity than the masked regions. The implanted polycide layer is then annealed by RTA and patterned to form the conductors, gate electrodes and interconnects from the low resistivity regions and resistive components of an integrated circuit from the high resistivity regions. The capability of selecting from high and low resistive regions in a single polycide layer permits the design of resistive components with smaller areas than would be permitted if the resistive components were formed of a single low resistivity layer. This extra degree of freedom permits the designer to optimize device density and device performance without compromising either. The procedure utilizes a additional masking step utilizing a block-out mask.
摘要翻译：一种形成多晶硅化物层的方法，其中硅化物层被覆盖地沉积在多晶硅层上并且通过掩模选择性离子注入以形成比掩蔽区域更高的电阻率的区域。然后将注入的多晶硅化合物层通过RTA进行退火并图案化以形成来自高电阻率区域的集成电路的低电阻率区域和电阻分量的导体，栅电极和互连。在单个多晶硅层中从高和低电阻区域中选择的能力允许设计具有比允许的更小面积的电阻元件，如果电阻元件由单个低电阻率层形成。这种额外的自由度允许设计人员优化设备密度和设备性能，而不会影响设备的性能。该过程利用一个附加掩蔽步骤利用封锁掩模。

16. 发明授权

US5807786A Method of making a barrier layer to protect programmable antifuse structure from damage during fabrication sequence 失效
标题翻译：制造阻挡层的方法，以保护可编程反熔丝结构免受制造过程中的损坏
公开(公告)号：US5807786A
公开(公告)日：1998-09-15
申请号：US902754
申请日：1997-07-30
申请人： Tzong-Sheng Chang
发明人： Tzong-Sheng Chang
IPC分类号： H01L21/768 , H01L23/525 , H01L21/44
CPC分类号： H01L21/76888 , H01L23/5252 , H01L2924/0002
摘要： A method for forming an antifuse interconnect structure, for a one-time fusible link, to be used with field-programmable gate arrays, has been developed. The process features the use of an amorphous silicon layer, used as the antifuse layer, with the amorphous silicon layer protected by a thin barrier layer, during the patterning procedure. The protected antifuse layer results in a reproducible thickness, and thus reproducible pulsing voltages, needed for rupturing of the antifuse layer. Planarization of an underlying metal plug, via an insulator refill procedure, offers a smooth surface for the overlying antifuse layer.
摘要翻译：已经开发了用于与现场可编程门阵列一起使用的用于一次性可熔链路的反熔丝互连结构的方法。该工艺的特征在于在图案化步骤期间使用非晶硅层作为反熔丝层，非晶硅层被薄的阻挡层保护。受保护的反熔丝层导致反熔丝层破裂所需的可再现厚度，并因此产生可再现的脉冲电压。通过绝缘体补充程序对底层金属插头进行平面化，为上覆反熔丝层提供了一个光滑的表面。

17. 发明申请

US20100081249A1 Method to reduce leakage in a protection diode structure 有权
标题翻译：减少保护二极管结构泄漏的方法
公开(公告)号：US20100081249A1
公开(公告)日：2010-04-01
申请号：US12592810
申请日：2009-12-03
申请人： Bor-Zen Tien , Tzong-Sheng Chang , Yung-Fu Shen , Jieh-Ting Chang
发明人： Bor-Zen Tien , Tzong-Sheng Chang , Yung-Fu Shen , Jieh-Ting Chang
IPC分类号： H01L21/762
CPC分类号： H01L29/861 , H01L27/0255 , H01L29/0607 , H01L29/6609 , Y10S438/91
摘要： A method for forming a protection diode utilizes processing operations and materials used in the formation of the CMOS integrated circuit device and provides a protection diode used in CMOS integrated circuit devices to direct charged particles to benign locations and prevent damage to the devices. The protection diode includes a well region of a first conductivity type formed in a surface of a semiconductor substrate, a heavily doped P-type impurity region disposed within the well region, a heavily doped N-type impurity region disposed within the well region and an STI structure interposed therebetween. A top surface of the STI structure extends above the surface. A silicide resistant block-out layer is formed over the STI structure and extends laterally beyond the STI structure, covering any counterdoped sections that may undesirably be formed in the substrate adjacent the STI structure during implantation operations.
摘要翻译：用于形成保护二极管的方法利用了用于形成CMOS集成电路器件的处理操作和材料，并且提供了用于CMOS集成电路器件中的保护二极管，以将带电粒子引导到良性位置并防止对器件的损坏。保护二极管包括形成在半导体衬底的表面中的第一导电类型的阱区，设置在阱区内的重掺杂P型杂质区，设置在阱区内的重掺杂N型杂质区和 STI结构。 STI结构的顶表面在表面上方延伸。在STI结构上方形成硅化物阻挡层，横向延伸超过STI结构，覆盖在植入操作期间可能不期望地形成在邻近STI结构的衬底中的任何反向部分。

18. 发明授权

US07663164B2 Semiconductor device with reduced leakage protection diode 有权
标题翻译：具有减少漏电保护二极管的半导体器件
公开(公告)号：US07663164B2
公开(公告)日：2010-02-16
申请号：US11044819
申请日：2005-01-26
申请人： Bor-Zen Tien , Tzong-Sheng Chang , Yung-Fu Shen , Jieh-Ting Chang
发明人： Bor-Zen Tien , Tzong-Sheng Chang , Yung-Fu Shen , Jieh-Ting Chang
IPC分类号： H01L27/10
CPC分类号： H01L29/861 , H01L27/0255 , H01L29/0607 , H01L29/6609 , Y10S438/91
摘要： A protection diode is used in a CMOS integrated circuit device to direct charged particles to benign locations and prevent damage to the device. The protection diode includes a well region of a first conductivity type formed in a surface of a semiconductor substrate, a heavily doped P-type impurity region disposed within the well region, a heavily doped N-type impurity region disposed within the well region and an STI structure interposed therebetween. A top surface of the STI structure extends above the surface. A silicide resistant block-out layer is formed over the STI structure and extends laterally beyond the STI structure, covering any counterdoped sections that may undesirably be formed in the substrate adjacent the STI structure during implantation operations. The method for forming the structure utilizes processing operations and materials used in the formation of the CMOS integrated circuit device.
摘要翻译：在CMOS集成电路器件中使用保护二极管，以将带电粒子引导到良性位置，并防止损坏器件。保护二极管包括形成在半导体衬底的表面中的第一导电类型的阱区，设置在阱区内的重掺杂P型杂质区，设置在阱区内的重掺杂N型杂质区和 STI结构。 STI结构的顶表面在表面上方延伸。在STI结构上方形成硅化物阻挡层，横向延伸超过STI结构，覆盖在植入操作期间可能不期望地形成在邻近STI结构的衬底中的任何反向部分。形成结构的方法利用了用于形成CMOS集成电路器件的处理操作和材料。

19. 发明授权

US06294448B1 Method to improve TiSix salicide formation 有权
标题翻译：改善TiSix自杀化合物形成的方法
公开(公告)号：US06294448B1
公开(公告)日：2001-09-25
申请号：US09483932
申请日：2000-01-18
申请人： Tzong-Sheng Chang , Hung-Chi Tsai , Bor-Zen Tien
发明人： Tzong-Sheng Chang , Hung-Chi Tsai , Bor-Zen Tien
IPC分类号： H01L2144
CPC分类号： H01L21/28518
摘要： A new method is provided for the formation of silicided layers over points of electrical contact that are required in MOSFET devices. The structure of the MOSFET gate electrode is formed, including LDD regions, gate spacers and source/drain regions. A layer of Resist Protective Oxide (RPO) is deposited over the structure and patterned leaving the RPO in place where the silicided layers are not to be formed and exposing surfaces on which salicided layers are to be formed. These surfaces are the surfaces of the substrate overlying the source and drain regions and the surface of the gate electrode. An extra As or BF2 implant is performed into the surface of the exposed regions after which the process of salicidation is performed following conventional processing steps.
摘要翻译：提供了一种新的方法，用于在MOSFET器件中需要的电接触点上形成硅化层。形成MOSFET栅电极的结构，包括LDD区，栅极间隔区和源极/漏极区。在该结构上沉积一层抗蚀保护氧化物（RPO），并将其图案化，使RPO保持在不要形成硅化物层的位置，并且要在其上形成水银层的暴露表面。这些表面是覆盖源极和漏极区域以及栅电极表面的衬底的表面。在暴露区域的表面进行额外的As或BF2植入物，之后在常规加工步骤之后执行盐化过程。

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