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11. 发明授权

US06512707B2 Semiconductor integrated circuit device allowing accurate evaluation of access time of memory core contained therein and access time evaluating method 有权
公开(公告)号：US06512707B2
公开(公告)日：2003-01-28
申请号：US09837164
申请日：2001-04-19
申请人： Manabu Miura , Makoto Hatakenaka
发明人： Manabu Miura , Makoto Hatakenaka
IPC分类号： G11C700
CPC分类号： G11C29/028 , G11C11/401 , G11C29/50 , G11C29/50012
摘要： An external clock signal is transmitted as a clock signal to a memory core through a first signal transmitting path. In response to activation of the clock signal CLK, memory core starts a read operation. Read data output from memory core is latched by a latch circuit. An external signal designating a latch timing is transmitted as a latch timing signal to the latch circuit through a second signal transmitting path. A delay circuit is provided in at least one of the first and second signal transmitting paths, so that the first and second signal transmitting paths come to have the same signal delay.

12. 发明授权

US06310815B1 Multi-bank semiconductor memory device suitable for integration with logic 失效
标题翻译：适合与逻辑集成的多存储半导体存储器件
公开(公告)号：US06310815B1
公开(公告)日：2001-10-30
申请号：US09131346
申请日：1998-08-07
申请人： Tadato Yamagata , Akira Yamazaki , Shigeki Tomishima , Yoshio Yukinari , Makoto Hatakenaka , Atsushi Miyanishi
发明人： Tadato Yamagata , Akira Yamazaki , Shigeki Tomishima , Yoshio Yukinari , Makoto Hatakenaka , Atsushi Miyanishi
IPC分类号： G11C800
CPC分类号： G11C5/14 , G11C8/12
摘要： Subbanks are arranged in four regions of a DRAM macro having a rectangular shape, bank control circuits are arranged in a prescribed region between these subbanks, and internal read/write data buses are arranged in a region different from the region where the bank control circuits are arranged. Since there is no crossing of the bank control circuits and the internal read/write data buses, the bank control circuits can be efficiently arranged to reduce the layout area. Accordingly, a semiconductor integrated circuit device including multi-bank memories which operates stably at high speed can be provided without increase of an area occupied by a chip.
摘要翻译：子行排列在具有矩形形状的DRAM宏的四个区域中，组控制电路布置在这些子行之间的规定区域中，并且内部读/写数据总线布置在与存储体控制电路的区域不同的区域中安排。由于银行控制电路和内部读/写数据总线没有交叉，因此可以有效地布置存储体控制电路以减少布局面积。因此，可以在不增加芯片占有面积的情况下提供包括以高速稳定运行的多存储体存储器的半导体集成电路器件。

13. 发明授权

US06163493A Semiconductor integrated circuit device with large internal bus width, including memory and logic circuit 有权
标题翻译：具有内部总线宽度大的半导体集成电路器件，包括存储器和逻辑电路
公开(公告)号：US06163493A
公开(公告)日：2000-12-19
申请号：US208492
申请日：1998-12-10
申请人： Tadato Yamagata , Makoto Hatakenaka , Shigeki Tomishima , Akira Yamazaki
发明人： Tadato Yamagata , Makoto Hatakenaka , Shigeki Tomishima , Akira Yamazaki
IPC分类号： G11C11/407 , G11C5/14 , G11C11/4074 , G11C11/409 , H01L21/8242 , H01L27/108 , G11C7/00
CPC分类号： G11C11/4074 , G11C5/147
摘要： A first internal power supply circuit receiving an external power supply voltage for generating a first internal power supply voltage and a second internal power supply circuit receiving the external power supply voltage for generating a second internal power supply voltage are provided within a DRAM. A sense amplifier operates by the first internal power supply voltage. A write driver and a GIO line precharge circuit operate by the second internal power supply voltage. A peripheral circuit operates by the external power supply voltage. As a result, the sense amplifier and the peripheral circuit will not be affected by the operation of the write driver and the GIO line precharge circuit.
摘要翻译：接收用于产生第一内部电源电压的外部电源电压的第一内部电源电路和接收用于产生第二内部电源电压的外部电源电压的第二内部电源电路设置在DRAM内。读出放大器通过第一内部电源电压进行工作。写驱动器和GIO线预充电电路由第二内部电源电压工作。外围电路由外部电源供电。结果，读出放大器和外围电路不会受到写入驱动器和GIO线路预充电电路的操作的影响。

14. 发明授权

US5949268A Variable delay circuit for varying delay time and pulse width 失效
标题翻译：可变延迟电路，用于改变延迟时间和脉冲宽度
公开(公告)号：US5949268A
公开(公告)日：1999-09-07
申请号：US914803
申请日：1997-08-15
申请人： Manabu Miura , Makoto Hatakenaka
发明人： Manabu Miura , Makoto Hatakenaka
IPC分类号： H03K5/04 , H03K5/13 , H03K17/16 , H03K17/687
CPC分类号： H03K17/164 , H03K5/131
摘要： A variable delay circuit for controlling delay time includes P channel transistors connected in parallel, with respective source electrodes connected to a power supply, respective drain electrodes connected to an output terminal for providing delayed signal, and respective gate electrodes connected to respective control signal input terminals for receiving control signals. The circuit further includes N channel transistors with respective source electrodes connected to ground, respective drain electrodes connected to the output terminal, and respective gate electrode connected to the respective control signal input terminals. Identical or mutually inverted data signals or control signals are supplied to the respective gate electrodes of the P channel transistors and the respective gate electrodes of the N channel transistors.
摘要翻译：用于控制延迟时间的可变延迟电路包括并联连接的P沟道晶体管，各个源电极连接到电源，连接到用于提供延迟信号的输出端的相应漏电极以及连接到相应控制信号输入端的各个栅电极用于接收控制信号。电路还包括具有连接到地的各个源极的N沟道晶体管，连接到输出端的相应的漏极和连接到各个控制信号输入端的相应的栅电极。将相同或相互反转的数据信号或控制信号提供给P沟道晶体管的各个栅电极和N沟道晶体管的各个栅电极。

15. 发明授权

US5539344A Phase-locked circuit and interated circuit device 失效
标题翻译：锁相电路和集成电路器件
公开(公告)号：US5539344A
公开(公告)日：1996-07-23
申请号：US225885
申请日：1994-04-11
申请人： Makoto Hatakenaka
发明人： Makoto Hatakenaka
IPC分类号： G06F1/10 , G06F1/12 , G11C11/407 , H03L7/00 , H04L7/00 , H04L7/033
CPC分类号： H03L7/00 , G06F1/12
摘要： The objects are to speed up the operation of an integrated circuit device having a sequential circuit and increase margin of phase synchronization for performing data processing of time sequential circuit. The phase-locked circuit (57) is provided in the integrated circuit (50), and the clock signal (CK7) which is inputted from the outside through the phase-locked circuit is supplied to the sequential circuit (52). The data outputted from the sequential circuit (52) is fed back from the output end of the buffer (Bu56) to the phase-locked circuit (57). In the phase-locked circuit (57), the clock signal (CK7) inputted through the buffer (Bu50) and the output data of the sequential circuit (52) are compared in phase and the phase of the clock signal outputted to the sequential circuit (52) is adjusted so that the phases thereof agree. The output data (DO7) outputted from the sequential circuit (52) is not delayed with respect clock signal (CK7). Accordingly, the data processing in the integrated circuit (70) can be speeded up.
摘要翻译：目的是加快具有时序电路的集成电路装置的操作，并且增加用于执行时序电路的数据处理的相位同步的余量。锁相电路（57）设置在集成电路（50）中，并且通过锁相电路从外部输入的时钟信号（CK7）被提供给顺序电路（52）。从顺序电路（52）输出的数据从缓冲器（Bu56）的输出端反馈到锁相电路（57）。在锁相电路57中，通过缓冲器（Bu50）输入的时钟信号（CK7）和时序电路（52）的输出数据进行比较，输出到时序电路的时钟信号的相位（52）被调节，使得其相位一致。从时序电路（52）输出的输出数据（DO7）不依赖于时钟信号（CK7）延迟。因此，可以加快集成电路（70）中的数据处理。

16. 发明授权

US07984223B2 Information device including main processing circuit, interface circuit, and microcomputer 有权
标题翻译：信息设备包括主处理电路，接口电路和微机
公开(公告)号：US07984223B2
公开(公告)日：2011-07-19
申请号：US12659545
申请日：2010-03-12
申请人： Hideo Nagano , Kikuo Muramatsu , Masayuki Koyama , Tomoko Ando , Motoki Higashida , Takahiko Arakawa , Makoto Hatakenaka
发明人： Hideo Nagano , Kikuo Muramatsu , Masayuki Koyama , Tomoko Ando , Motoki Higashida , Takahiko Arakawa , Makoto Hatakenaka
IPC分类号： G06F13/14
CPC分类号： H04N5/04 , G09G5/006 , H04N5/775 , H04N5/85
摘要： An information device packaged in one package includes a main function unit and an interface function unit. The main function unit includes a main processing circuit for executing signal processing related to a main function in the information device and a first microcomputer for controlling the main processing circuit by executing a first firmware program. The interface function unit includes an interface function unit including a first interface circuit for receiving data from an exterior device located outside of the information device to provide to the main function unit, a second interface circuit for performing an authentication operation with the exterior device, a second microcomputer for controlling the first interface circuit, and a memory for storing a second firmware program for controlling the first interface circuit.
摘要翻译：包装在一个包装中的信息装置包括主功能单元和接口功能单元。主功能单元包括用于执行与信息装置中的主要功能相关的信号处理的主处理电路和用于通过执行第一固件程序来控制主处理电路的第一微型计算机。接口功能单元包括接口功能单元，其包括第一接口电路，用于从位于信息设备外部的外部设备接收数据，以向主功能单元提供用于与外部设备进行认证操作的第二接口电路，用于控制第一接口电路的第二微型计算机，以及用于存储用于控制第一接口电路的第二固件程序的存储器。

17. 发明申请

US20100191883A1 INFORMATION DEVICE INCLUDING MAIN PROCESSING CIRCUIT, INTERFACE CIRCUIT, AND MICROCOMPUTER 有权
标题翻译：包括主处理电路，接口电路和微处理器的信息设备
公开(公告)号：US20100191883A1
公开(公告)日：2010-07-29
申请号：US12659545
申请日：2010-03-12
申请人： Hideo Nagano , Kikuo Muramatsu , Masayuki Koyama , Tomoko Ando , Motoki Higashida , Takahiko Arakawa , Makoto Hatakenaka
发明人： Hideo Nagano , Kikuo Muramatsu , Masayuki Koyama , Tomoko Ando , Motoki Higashida , Takahiko Arakawa , Makoto Hatakenaka
IPC分类号： G06F13/42 , H04L9/32 , G06F13/00 , H04N9/475
CPC分类号： H04N5/04 , G09G5/006 , H04N5/775 , H04N5/85
摘要： An information device packaged in one package includes a main function unit and an interface function unit. The main function unit includes a main processing circuit for executing signal processing related to a main function in the information device and a first microcomputer for controlling the main processing circuit by executing a first firmware program. The interface function unit includes an interface function unit including a first interface circuit for receiving data from an exterior device located outside of the information device to provide to the main function unit, a second interface circuit for performing an authentication operation with the exterior device, a second microcomputer for controlling the first interface circuit, and a memory for storing a second firmware program for controlling the first interface circuit.
摘要翻译：包装在一个包装中的信息装置包括主功能单元和接口功能单元。主功能单元包括用于执行与信息装置中的主要功能相关的信号处理的主处理电路和用于通过执行第一固件程序来控制主处理电路的第一微型计算机。接口功能单元包括接口功能单元，其包括第一接口电路，用于从位于信息设备外部的外部设备接收数据，以向主功能单元提供用于与外部设备进行认证操作的第二接口电路，用于控制第一接口电路的第二微型计算机，以及用于存储用于控制第一接口电路的第二固件程序的存储器。

18. 发明申请

US20070091122A1 Information device 有权
标题翻译：信息设备
公开(公告)号：US20070091122A1
公开(公告)日：2007-04-26
申请号：US11584550
申请日：2006-10-23
申请人： Hideo Nagano , Kikuo Muramatsu , Masayuki Koyama , Tomoko Ando , Motoki Higashida , Takahiko Arakawa , Makoto Hatakenaka
发明人： Hideo Nagano , Kikuo Muramatsu , Masayuki Koyama , Tomoko Ando , Motoki Higashida , Takahiko Arakawa , Makoto Hatakenaka
IPC分类号： G09G5/00
CPC分类号： H04N5/04 , G09G5/006 , H04N5/775 , H04N5/85
摘要： An information device includes a main processing circuit for executing signal processing related to a main function in the information device, a main microcomputer for controlling the main processing circuit, a receiver circuit for interfacing with the outside of the information device, and an interface microcomputer for controlling the receiver circuit, the interface microcomputer being provided separately from the main microcomputer.
摘要翻译：信息装置包括用于执行与信息装置中的主要功能相关的信号处理的主处理电路，用于控制主处理电路的主微型计算机，用于与信息装置的外部进行接口的接收机电路，以及用于控制接收机电路，接口微型计算机与主微型计算机分开设置。

19. 发明授权

US06756803B2 Semiconductor device downsizing its built-in driver 失效
标题翻译：半导体器件缩小其内置驱动器
公开(公告)号：US06756803B2
公开(公告)日：2004-06-29
申请号：US10330072
申请日：2002-12-30
申请人： Manabu Miura , Makoto Hatakenaka , Takekazu Yamashita
发明人： Manabu Miura , Makoto Hatakenaka , Takekazu Yamashita
IPC分类号： G01R3102
CPC分类号： G01R31/2884 , H01L2224/05554 , H01L2224/48091 , H01L2224/48137 , H01L2224/49175 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device includes a first pad, a second pad, a first buffer and a second buffer. The first pad is connected to another semiconductor device in a multi-chip package, and the second pad makes a probing connection in a wafer test. The first buffer drives the another semiconductor device connected to the first pad. The second buffer, being driven by the first buffer, drives a load capacitance of a tester connected to the second pad with the driving power greater than the driving power of the first buffer, and has its active/inactive state controlled by a control signal. The semiconductor device can provide the driving power necessary for the wafer test, and drive the another semiconductor device with preventing generation of drive noise and suppressing current consumption in the normal operation of the multi-chip package.
摘要翻译：半导体器件包括第一焊盘，第二焊盘，第一缓冲器和第二缓冲器。第一焊盘以多芯片封装连接到另一半导体器件，并且第二焊盘在晶片测试中进行探测连接。第一缓冲器驱动连接到第一焊盘的另一个半导体器件。由第一缓冲器驱动的第二缓冲器以大于第一缓冲器的驱动功率的驱动功率驱动连接到第二焊盘的测试仪的负载电容，并且由控制信号控制其主动/不活动状态。半导体器件可以提供晶片测试所需的驱动功率，并驱动另一半导体器件，防止产生驱动噪声并抑制多芯片封装的正常工作中的电流消耗。

20. 发明授权

US07237175B2 Memory circuit 有权
标题翻译：存储电路
公开(公告)号：US07237175B2
公开(公告)日：2007-06-26
申请号：US10193319
申请日：2002-07-12
申请人： Makoto Hatakenaka , Koji Nii , Atsuo Mangyo , Takeshi Fujino
发明人： Makoto Hatakenaka , Koji Nii , Atsuo Mangyo , Takeshi Fujino
IPC分类号： G11C29/00
CPC分类号： G06F11/1012
摘要： When to a memory cell array 21 a read/write operation is performed of the 7-bit data in which parity bits of 3 bits are added to data of 4 bits, an error correction is carried out in concern to each of the 7-bit data. The memory cell array is divided into memory units 31 to 37 each of which has four bits which are arranged along a direction of a word line. On writing the 7-bit data in the memory cell array, bits of the 7-bit data that are different from one another are written as written bit data along the direction of the word line in the memory units 31 to 37, respectively. In the 7-bit data, the written bit data has an interval of four bits. Error correcting circuits performs an error correction of the 7-bit data in each of the 7-bit data.
摘要翻译：对于存储单元阵列21，对其中将3位的奇偶校验位加到4位的数据的7位数据执行读/写操作，关于7位的每一位执行错误校正数据。存储单元阵列被分成存储器单元31至37，每个存储单元具有沿着字线的方向布置的四位。在将7位数据写入存储单元阵列时，7位数据彼此不同的位被分别写入存储单元31至37中的字线方向的写入位数据。在7位数据中，写入位数据的间隔为4位。误差校正电路对7位数据中的每一个执行7位数据的纠错。

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