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11. 发明申请

US20070293038A1 Method of manufacturing multilayer wiring substrate, and multilayer wiring substrate 审中-公开
公开(公告)号：US20070293038A1
公开(公告)日：2007-12-20
申请号：US11890892
申请日：2007-08-08
申请人： Hiroshi Asami , Hidetoshi Kusano , Yuji Nishitani , Ken Orui
发明人： Hiroshi Asami , Hidetoshi Kusano , Yuji Nishitani , Ken Orui
IPC分类号： H01L21/4763
CPC分类号： H05K3/4694 , H01L21/4846 , H01L21/4857 , H01L23/49833 , H01L2924/0002 , H01L2924/09701 , H05K3/0023 , H05K3/205 , H05K3/4617 , H05K3/4623 , H05K2201/0195 , H05K2201/09536 , H05K2201/09881 , H05K2201/09972 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49155 , Y10T29/49165 , H01L2924/00
摘要： The present invention provides a method of manufacturing a multilayer wiring substrate, which can preserve the dimensional stability of a conductor pattern at a fine pitch, solve the restriction on a process from the viewpoint of material selection, and further reduce a manufacturing cost, and a multilayer wiring substrate. A second wiring substrate formed on a supporting sheet made of metal and an adhesive layer are partially stacked on a predetermined region of a first wiring substrate by using the supporting sheet. After the lamination of the second wiring substrate, the supporting sheet is finally etched and removed. The second wiring substrate is stacked only on the portion required to be multilayered on the first wiring substrate to thereby reduce the amount of the construction material of the second wiring substrate.

12. 发明授权

US06637105B1 Method of manufacturing a multilayer printed wiring board 失效
标题翻译：制造多层印刷线路板的方法
公开(公告)号：US06637105B1
公开(公告)日：2003-10-28
申请号：US09637859
申请日：2000-08-15
申请人： Yoshio Watanabe , Nobuyuki Yasuda , Hironori Mihono , Yuji Nishitani
发明人： Yoshio Watanabe , Nobuyuki Yasuda , Hironori Mihono , Yuji Nishitani
IPC分类号： H01K310
CPC分类号： H05K3/4614 , H05K3/321 , H05K3/4046 , H05K3/4069 , H05K3/4623 , H05K2201/0367 , H05K2201/0394 , H05K2201/09536 , H05K2201/0959 , H05K2201/09827 , H05K2201/10378 , H05K2203/063 , H05K2203/0733 , H05K2203/1157 , Y10T29/49128 , Y10T29/49155 , Y10T29/49165
摘要： The invention provides a high-density multilayer printed wiring board and a method for manufacturing a multilayer printed wiring board having high-density wiring that is formed easily. A method for manufacturing a multilayer printed wiring board formed by laminating a plurality of laminates comprises a step for forming a conduction hole on a laminate comprising an insulating board having both sides on which conductive films are formed, a step for electrically connecting between both sides of said laminate through the above-mentioned conduction hole and planarizing the surface, a step for patterning the above-mentioned conductive film desiredly and forming a projection member at a desired position of the above-mentioned conductive film, a step for laminating bonding members having a through hole to which the above-mentioned projection member is inserted, which is served for bonding between the above-mentioned laminates, and the above-mentioned laminates alternately with insertion of the above-mentioned projection member into the above-mentioned throughhole, and a step for press-molding the above-mentioned laminated laminates and bonding members with heating.
摘要翻译：本发明提供了一种高密度多层印刷线路板和一种容易形成高密度布线的多层印刷布线板的制造方法。制造通过层叠多个层叠体而形成的多层印刷布线板的方法包括在层叠体上形成导电孔的步骤，该叠层包括具有两侧的绝缘板，形成有导电膜的步骤，所述层压体通过上述导电孔并使表面平坦化，所需的上述导电膜图案化步骤和在上述导电膜的所需位置形成突起构件的步骤，用于层压具有上述凸起构件插入到上述通孔中的用于上述层叠体之间的粘合的上述凸起构件和上述层压体的通孔交替地插入上述通孔中，并且用于加热上述层叠层叠体和粘接部件的压制成形工序。

13. 发明授权

US08315011B2 Disk drive device improved in stiffness of fluid dynamic bearing 失效
标题翻译：磁盘驱动装置提高了流体动力轴承的刚度
公开(公告)号：US08315011B2
公开(公告)日：2012-11-20
申请号：US12769559
申请日：2010-04-28
申请人： Yuji Nishitani
发明人： Yuji Nishitani
IPC分类号： G11B17/02 , H02K5/16
CPC分类号： G11B19/2036
摘要： A disk drive device includes a bearing unit and a drive unit. The bearing unit includes: a shaft; a sleeve configured to allow relative rotation, with the shaft as the axis; a flange projected in the radial direction of the shaft and configured to rotate integrally with the shaft; a flange housing space portion provided continuously from the sleeve and configured to rotatably house the flange; a counter plate structured with both a first surface, which faces the end surface in the axial direction of the flange and seals the flange housing space portion, and a second surface that is opposite to the first surface. The projected dimension of the flange is designed to be larger than the wall thickness of the flange surrounding wall portion in the radial direction of the flange, the flange surrounding wall portion defining the flange housing space portion.
摘要翻译：磁盘驱动装置包括轴承单元和驱动单元。轴承单元包括：轴; 套筒构造成允许相对旋转，以轴为轴; 沿所述轴的径向方向突出并且构造成与所述轴一体地旋转的凸缘; 凸缘容纳空间部分，其从所述套筒连续地设置并且构造成可旋转地容纳所述凸缘; 对置板，其构造为具有面向凸缘的轴向端面的第一表面并密封凸缘容纳空间部分的第二表面和与第一表面相对的第二表面。凸缘的突出尺寸被设计成大于凸缘的径向方向上围绕壁部的凸缘的壁厚，凸缘围壁部分限定凸缘容纳空间部分。

14. 发明授权

US07436682B2 Wiring board, electronic component mounting structure, and electronic component mounting method 有权
标题翻译：接线板，电子部件安装结构和电子部件安装方法
公开(公告)号：US07436682B2
公开(公告)日：2008-10-14
申请号：US11600928
申请日：2006-11-16
申请人： Yuji Nishitani , Tomoshi Ohde
发明人： Yuji Nishitani , Tomoshi Ohde
IPC分类号： H05K7/12
CPC分类号： H05K3/3436 , H01L23/49811 , H01L23/49838 , H01L24/10 , H01L24/13 , H01L24/81 , H01L2224/05568 , H01L2224/05573 , H01L2224/13 , H01L2224/13012 , H01L2224/13099 , H01L2224/13111 , H01L2224/16225 , H01L2224/81143 , H01L2224/81193 , H01L2224/8121 , H01L2224/81815 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H05K3/3463 , H05K2201/094 , H05K2203/048 , Y02P70/613 , H01L2924/01029 , H01L2924/01047 , H01L2924/00 , H01L2224/05599
摘要： A flip chip mounting method for improving the accuracy of positioning of a semiconductor chip and avoiding a short circuit between protruding electrodes even when the protruding electrodes are formed at smaller spacings. The method comprises: placing a semiconductor chip on a wiring board, the semiconductor chip having protruding electrodes formed at a relatively small spacing and at a relatively large spacing, the wiring board having electrode pads corresponding to the respective protruding electrodes and solder pieces formed on the respective pads; heating the semiconductor chip and the wiring board to a temperature at which only the solder pieces on the electrode pads of greater spacing melt; performing self alignment of the semiconductor chip by the melted solder pieces; and heating the semiconductor chip and the wiring board further to a temperature at which the protruding electrodes and the solder pieces on the electrode pads of smaller spacing melt.
摘要翻译：一种用于提高半导体芯片的定位精度并避免突出电极之间的短路的倒装芯片安装方法，即使当突出电极以较小的间隔形成时。所述方法包括：将半导体芯片放置在布线板上，所述半导体芯片具有形成在相对较小间隔和相对较大间隔的突出电极，所述布线板具有对应于各个突出电极的电极焊盘和形成在各自的垫片将半导体芯片和布线板加热至只有较大间隔的电极焊盘上的焊料块熔化的温度; 通过熔融的焊料进行半导体芯片的自对准; 并且将半导体芯片和布线板进一步加热到间隔较小的电极焊盘上的突出电极和焊料片熔化的温度。

15. 发明授权

US07420127B2 Method of manufacturing multilayer wiring substrate, and multilayer wiring substrate 失效
标题翻译：多层布线基板的制造方法以及多层布线基板
公开(公告)号：US07420127B2
公开(公告)日：2008-09-02
申请号：US11644143
申请日：2006-12-22
申请人： Hiroshi Asami , Hidetoshi Kusano , Yuji Nishitani , Ken Orui
发明人： Hiroshi Asami , Hidetoshi Kusano , Yuji Nishitani , Ken Orui
IPC分类号： H05K1/02
CPC分类号： H05K3/4694 , H01L21/4846 , H01L21/4857 , H01L23/49833 , H01L2924/0002 , H01L2924/09701 , H05K3/0023 , H05K3/205 , H05K3/4617 , H05K3/4623 , H05K2201/0195 , H05K2201/09536 , H05K2201/09881 , H05K2201/09972 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49155 , Y10T29/49165 , H01L2924/00
摘要： The present invention provides a method of manufacturing a multilayer wiring substrate, which can preserve the dimensional stability of a conductor pattern at a fine pitch, solve the restriction on a process from the viewpoint of material selection, and further reduce a manufacturing cost, and a multilayer wiring substrate. A second wiring substrate formed on a supporting sheet made of metal and an adhesive layer are partially stacked on a predetermined region of a first wiring substrate by using the supporting sheet. After the lamination of the second wiring substrate, the supporting sheet is finally etched and removed. The second wiring substrate is stacked only on the portion required to be multilayered on the first wiring substrate to thereby reduce the amount of the construction material of the second wiring substrate.
摘要翻译：本发明提供一种制造多层布线基板的方法，其可以以细间距保持导体图案的尺寸稳定性，从材料选择的角度解决对工艺的限制，并且进一步降低制造成本，并且多层布线基板。形成在由金属制成的支撑片和粘合剂层上的第二布线基板通过使用支撑片部分堆叠在第一布线基板的预定区域上。在第二布线基板的层叠之后，最后蚀刻并去除支撑片。第二布线基板仅堆叠在第一布线基板上需要多层的部分上，从而减少第二布线基板的结构材料的量。

16. 发明申请

US20080185712A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080185712A1
公开(公告)日：2008-08-07
申请号：US11968840
申请日：2008-01-03
申请人： Fujio Kanayama , Tomoshi Ohde , Mitsuru Adachi , Tetsunori Niimi , Hidetoshi Kusano , Yuji Nishitani
发明人： Fujio Kanayama , Tomoshi Ohde , Mitsuru Adachi , Tetsunori Niimi , Hidetoshi Kusano , Yuji Nishitani
IPC分类号： H01L23/36 , H01L21/56
CPC分类号： H01L23/315 , H01L21/565 , H01L23/055 , H01L23/3121 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/19041 , H01L2924/00012 , H01L2924/00 , H01L2224/0401
摘要： A semiconductor device is provided in which the effect of the heat generated by a flip-chip mounted semiconductor on resin is suppressed. The semiconductor device includes: a substrate; a semiconductor chip which is mounted on the substrate with a front surface of the semiconductor chip facing downward; and a molding resin layer provided on a semiconductor chip-mounted surface of the substrate so as to be spaced apart from the semiconductor chip and to surround the semiconductor chip. In addition, the upper surface of the molding resin layer is positioned higher than the rear surface of the semiconductor chip.
摘要翻译：提供一种半导体器件，其中抑制由倒装芯片安装的半导体产生的热对树脂的影响。半导体器件包括：衬底; 半导体芯片，其安装在基板上，半导体芯片的前表面朝下; 以及模塑树脂层，设置在与半导体芯片间隔开并围绕半导体芯片的基板的半导体芯片安装表面上。此外，成型树脂层的上表面位于比半导体芯片的后表面更高的位置。

17. 发明申请

US20070119618A1 Wiring board, electronic component mounting structure, and electronic component mounting method 有权
标题翻译：接线板，电子部件安装结构和电子部件安装方法
公开(公告)号：US20070119618A1
公开(公告)日：2007-05-31
申请号：US11600928
申请日：2006-11-16
申请人： Yuji Nishitani , Tomoshi Ohde
发明人： Yuji Nishitani , Tomoshi Ohde
IPC分类号： H05K1/16
CPC分类号： H05K3/3436 , H01L23/49811 , H01L23/49838 , H01L24/10 , H01L24/13 , H01L24/81 , H01L2224/05568 , H01L2224/05573 , H01L2224/13 , H01L2224/13012 , H01L2224/13099 , H01L2224/13111 , H01L2224/16225 , H01L2224/81143 , H01L2224/81193 , H01L2224/8121 , H01L2224/81815 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H05K3/3463 , H05K2201/094 , H05K2203/048 , Y02P70/613 , H01L2924/01029 , H01L2924/01047 , H01L2924/00 , H01L2224/05599
摘要： A flip chip mounting method for improving the accuracy of positioning of a semiconductor chip and avoiding a short circuit between protruding electrodes even when the protruding electrodes are formed at smaller spacings. The method comprises: placing a semiconductor chip on a wiring board, the semiconductor chip having protruding electrodes formed at a relatively small spacing and at a relatively large spacing, the wiring board having electrode pads corresponding to the respective protruding electrodes and solder pieces formed on the respective pads; heating the semiconductor chip and the wiring board to a temperature at which only the solder pieces on the electrode pads of greater spacing melt; performing self alignment of the semiconductor chip by the melted solder pieces; and heating the semiconductor chip and the wiring board further to a temperature at which the protruding electrodes and the solder pieces on the electrode pads of smaller spacing melt.
摘要翻译：一种用于提高半导体芯片的定位精度并避免突出电极之间的短路的倒装芯片安装方法，即使当突出电极以较小的间隔形成时。所述方法包括：将半导体芯片放置在布线板上，所述半导体芯片具有形成在相对较小间隔和相对较大间隔的突出电极，所述布线板具有对应于各个突出电极的电极焊盘和形成在各自的垫片将半导体芯片和布线板加热至只有较大间隔的电极焊盘上的焊料块熔化的温度; 通过熔融的焊料进行半导体芯片的自对准; 并且将半导体芯片和布线板进一步加热到间隔较小的电极焊盘上的突出电极和焊料片熔化的温度。

18. 发明申请

US20050142852A1 Method of manufacturing multilayer wiring substrate, and multilayer wiring substrate 失效
标题翻译：多层布线基板的制造方法以及多层布线基板
公开(公告)号：US20050142852A1
公开(公告)日：2005-06-30
申请号：US11063131
申请日：2005-02-22
申请人： Hiroshi Asami , Hidetoshi Kusano , Yuji Nishitani , Ken Orui
发明人： Hiroshi Asami , Hidetoshi Kusano , Yuji Nishitani , Ken Orui
IPC分类号： H05K3/22 , H01L23/12 , H05K3/00 , H05K3/20 , H05K3/46 , H01L21/4763 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H05K3/4694 , H01L21/4846 , H01L21/4857 , H01L23/49833 , H01L2924/0002 , H01L2924/09701 , H05K3/0023 , H05K3/205 , H05K3/4617 , H05K3/4623 , H05K2201/0195 , H05K2201/09536 , H05K2201/09881 , H05K2201/09972 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49155 , Y10T29/49165 , H01L2924/00
摘要： The present invention provides a method of manufacturing a multilayer wiring substrate, which can preserve the dimensional stability of a conductor pattern at a fine pitch, solve the restriction on a process from the viewpoint of material selection, and further reduce a manufacturing cost, and a multilayer wiring substrate. A second wiring substrate formed on a supporting sheet made of metal and an adhesive layer are partially stacked on a predetermined region of a first wiring substrate by using the supporting sheet. After the lamination of the second wiring substrate, the supporting sheet is finally etched and removed. The second wiring substrate is stacked only on the portion required to be multilayered on the first wiring substrate to thereby reduce the amount of the construction material of the second wiring substrate.
摘要翻译：本发明提供一种制造多层布线基板的方法，其可以以细间距保持导体图案的尺寸稳定性，从材料选择的角度解决对工艺的限制，并且进一步降低制造成本，并且多层布线基板。形成在由金属制成的支撑片和粘合剂层上的第二布线基板通过使用支撑片部分堆叠在第一布线基板的预定区域上。在第二布线基板的层叠之后，最后蚀刻并去除支撑片。第二布线基板仅堆叠在第一布线基板上需要多层的部分上，从而减少第二布线基板的结构材料的量。

19. 发明申请

US20050056445A1 Junction structure and junction method for conductive projection 有权
标题翻译：导电投影的结结构和接合方法
公开(公告)号：US20050056445A1
公开(公告)日：2005-03-17
申请号：US10802188
申请日：2004-03-17
申请人： Ken Orui , Hiroko Jinno , Yuji Nishitani , Hiroshi Asami
发明人： Ken Orui , Hiroko Jinno , Yuji Nishitani , Hiroshi Asami
IPC分类号： H01L23/12 , H01L21/60 , H01L23/32 , H02G3/08 , H05K3/34
CPC分类号： H05K3/3452 , H01L2224/10126 , H05K3/3478 , H05K2201/10734 , H05K2201/10977 , H05K2203/041 , H05K2203/043 , H05K2203/0594 , Y10T29/49147
摘要： To provide a junction structure and a junction method for conductive projection advantageous in that a required reinforcement strength can be obtained while suppressing the amount of a reinforcing resin material supplied to prevent warpage due to curing shrinkage. A conductive projection is joined to the surface of a conductor portion formed at the same level as that of the surface of the insulating layer so that a root portion of the projection is surrounded by a fillet-form resin material. The resin material contains an activator which assists in the junction between the conductive projection and the conductor portion when the resin material is in an uncured state, and is fused by heating to wet and rise the root portion of the conductive projection so as to be in a fillet form. The resin material is cured by an ultraviolet light while excluding the resin material on the conductor portion.
摘要翻译：提供一种用于导电突起的接合结构和接合方法，其优点在于可以获得所需的增强强度，同时抑制供应的增强树脂材料的量以防止由于固化收缩引起的翘曲。导电突起与形成在与绝缘层的表面相同水平面的导体部分的表面接合，使得突起的根部被圆角状的树脂材料包围。树脂材料含有活化剂，当树脂材料处于未固化状态时，其有助于导电突起与导体部分之间的接合，并通过加热熔化并使导电突起的根部上升，使其处于一个圆角形状。树脂材料通过紫外线固化，同时排除导体部分上的树脂材料。

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