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11. 发明授权

US5196909A Capacitor for DRAM cell 失效
标题翻译： DRAM单元电容器
公开(公告)号：US5196909A
公开(公告)日：1993-03-23
申请号：US697227
申请日：1991-05-07
申请人： Tsiu C. Chan , Frank R. Bryant
发明人： Tsiu C. Chan , Frank R. Bryant
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10844 , H01L27/10817 , H01L28/40
摘要： A capacitor suitable for use with a DRAM memory cell is composed of multiple layers of polycrystalline silicon. The storage node is formed from a polycrystalline silicon layer sandwiched between two polysilicon ground plate layers. Such a structure nearly doubles the capacitance for a given chip surface area used. First the bottom polycrystalline silicon plate layer is fabricated, followed by an isolation step and fabrication of the storage node polycrystalline silicon layer. Following another isolation step, the polycrystalline silicon top plate layer is then formed and connected to the bottom plate layer.
摘要翻译：适用于DRAM存储单元的电容器由多层多晶硅组成。存储节点由夹在两个多晶硅接地板层之间的多晶硅层形成。这种结构对于所使用的给定芯片表面积几乎使电容增加一倍。首先制造底部多晶硅板层，然后进行隔离步骤和存储节点多晶硅层的制造。在另一隔离步骤之后，然后形成多晶硅顶板层并将其连接到底板层。

12. 发明授权

US5914518A Method of forming a metal contact to landing pad structure in an integrated circuit 失效
公开(公告)号：US5914518A
公开(公告)日：1999-06-22
申请号：US759759
申请日：1996-12-03
申请人： Loi N. Nguyen , Frank R. Bryant
发明人： Loi N. Nguyen , Frank R. Bryant
IPC分类号： H01L21/28 , H01L21/285 , H01L21/768 , H01L21/8239 , H01L23/485 , H01L23/522 , H01L23/528 , H01L27/02 , H01L29/00
CPC分类号： H01L21/28 , H01L21/28525 , H01L21/76895 , H01L23/485 , H01L23/5226 , H01L23/5283 , H01L27/0248 , H01L27/1052 , H01L2924/0002
摘要： A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A landing pad is formed over the first dielectric layer and in the opening. The landing pad preferably comprises a doped polysilicon layer disposed in the first opening and over a portion of the first dielectric layer. The landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A second dielectric layer having an opening therethrough is formed over the landing pad having an opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the contact opening. The conductive contact will electrically connect with the diffused region through the landing pad. Misalignment of the conductive contact opening over the landing pad may be tolerated without invading design rules. Additionally, the landing pad will enhance planarization to provide for better step coverage of the metal contact in the second opening.

13. 发明授权

US5448091A Method of making contact alignment for nonvolatile memory devices 失效
标题翻译：非易失性存储器件接触对准方法
公开(公告)号：US5448091A
公开(公告)日：1995-09-05
申请号：US307475
申请日：1994-09-16
申请人： Frank R. Bryant , Tsiu C. Chan
发明人： Frank R. Bryant , Tsiu C. Chan
IPC分类号： G11C17/00 , H01L21/768 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/68
CPC分类号： H01L21/76802 , H01L27/115 , Y10S257/90
摘要： A layout and fabrication technique for EPROMs and similar devices includes a preferred technique for partially self-aligning bit line contacts. In addition, a self-aligned, buried Vss line is provided which is in contact with the substrate for its entire length. This provides a highly conductive Vss line, allowing the size of such line to be diminished. The use of a buried Vss contact line and a partially self-aligned bit line contact contributes to a device layout having minimum cell sizes for a given feature size.
摘要翻译： EPROM和类似器件的布局和制造技术包括用于部分自对准位线触点的优选技术。另外，提供了自对准埋置的Vss线，其与衬底的整个长度接触。这提供了高导电性Vss线，允许这种线的尺寸减小。使用埋入的Vss接触线和部分自对准位线接触有助于针对给定特征尺寸具有最小单元尺寸的器件布局。

14. 发明授权

US5426065A Method of making transistor devices in an SRAM cell 失效
标题翻译：在SRAM单元中制造晶体管器件的方法
公开(公告)号：US5426065A
公开(公告)日：1995-06-20
申请号：US159462
申请日：1993-11-30
申请人： Tsiu C. Chan , Frank R. Bryant
发明人： Tsiu C. Chan , Frank R. Bryant
IPC分类号： H01L21/336 , H01L21/8244 , H01L27/10 , H01L27/11 , H01L29/78 , H01L21/8229
CPC分类号： H01L27/11 , Y10S148/163
摘要： An SRAM memory cell having first and second transfer gate transistors. The first transfer gate transistor includes a first source/drain connected to a bit line and the second transfer gate transistor has a first source/drain connected to a complement bit line. Each transfer gate transistor has a gate connected to a word line. The SRAM memory cell also includes first and second pull-down transistors configured as a storage latch. The first pull-down transistor has a first source/drain connected to a second source/drain of said first transfer gate transistor; the second pull-down transistor has a first source/drain connected to a second source/drain of said second transfer gate transistor. Both first and second pull-down transistors have a second source/drain connected to a power supply voltage node. The first and second transfer gate transistors each include a gate oxide layer having a first thickness, and the first and second pull-down transistors each include a gate oxide layer having a second thickness, wherein and the first thickness is different from the second thickness.
摘要翻译：一种具有第一和第二传输门晶体管的SRAM存储单元。第一传输门晶体管包括连接到位线的第一源极/漏极，第二传输门晶体管具有连接到补码位线的第一源极/漏极。每个传输门晶体管具有连接到字线的栅极。 SRAM存储单元还包括被配置为存储锁存器的第一和第二下拉晶体管。第一下拉晶体管具有连接到所述第一传输栅极晶体管的第二源极/漏极的第一源极/漏极; 所述第二下拉晶体管具有连接到所述第二传输栅极晶体管的第二源极/漏极的第一源极/漏极。第一和第二下拉晶体管都具有连接到电源电压节点的第二源极/漏极。第一和第二传输门晶体管各自包括具有第一厚度的栅极氧化物层，并且第一和第二下拉晶体管各自包括具有第二厚度的栅极氧化物层，其中第一厚度不同于第二厚度。

15. 发明授权

US5376571A Method of making contact alignment for nonvolatile memory devices 失效
标题翻译：非易失性存储器件接触对准方法
公开(公告)号：US5376571A
公开(公告)日：1994-12-27
申请号：US118843
申请日：1993-09-10
申请人： Frank R. Bryant , Tsiu C. Chan
发明人： Frank R. Bryant , Tsiu C. Chan
IPC分类号： G11C17/00 , H01L21/768 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/441
CPC分类号： H01L21/76802 , H01L27/115 , Y10S257/90
摘要： A layout and fabrication technique for EPROMs and similar devices includes a preferred technique for partially self-aligning bit line contacts. In addition, a self-aligned, buried Vss line is provided which is in contact with the substrate for its entire length. This provides a highly conductive Vss line, allowing the size of such line to be diminished. The use of a buried Vss contact line and a partially self-aligned bit line contact contributes to a device layout having minimum cell sizes for a given feature size.
摘要翻译： EPROM和类似器件的布局和制造技术包括用于部分自对准位线触点的优选技术。另外，提供了自对准埋置的Vss线，其与衬底的整个长度接触。这提供了高导电性Vss线，允许这种线的尺寸减小。使用埋入的Vss接触线和部分自对准位线接触有助于针对给定特征尺寸具有最小单元尺寸的器件布局。

16. 发明授权

US5310692A Method of forming a MOSFET structure with planar surface 失效
标题翻译：形成具有平面表面的MOSFET结构的方法
公开(公告)号：US5310692A
公开(公告)日：1994-05-10
申请号：US889822
申请日：1992-05-29
申请人： Tsiu C. Chan , Frank R. Bryant
发明人： Tsiu C. Chan , Frank R. Bryant
IPC分类号： H01L21/76 , H01L21/28 , H01L21/3105 , H01L21/32 , H01L21/762 , H01L29/423 , H01L29/49 , H01L29/78 , H01L21/265
CPC分类号： H01L29/4933 , H01L21/28123 , H01L21/31055 , H01L21/32 , H01L21/76202 , H01L29/42376 , H01L2924/0002
摘要： A method is provided for a planar surface of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A conductive layer is formed over a substrate. A silicon nitride layer is formed over the conductive layer. A photoresist layer is then formed and patterned over the silicon nitride layer. The silicon nitride layer and the conductive layer are etched to form an opening exposing a portion of the substrate. The photoresist layer is then removed. The exposed substrate and a portion of the conductive layer exposed along the sidewalls in the opening are oxidized. An planarizing insulating layer such as spin-on-glass is formed over the silicon nitride layer and in the opening. The insulating layer is etched back to expose the silicon nitride wherein an upper surface of the insulating layer is level with an upper surface of the conductive layer. The silicon nitride layer is then removed. A planar silicide layer is then formed over the conductive layer.
摘要翻译：提供了一种用于半导体集成电路的平面的方法和根据该集成电路形成的集成电路。在衬底上形成导电层。在导电层上形成氮化硅层。然后在氮化硅层上形成并图案化光致抗蚀剂层。蚀刻氮化硅层和导电层以形成露出衬底的一部分的开口。然后除去光致抗蚀剂层。暴露的基板和沿开口侧壁暴露的导电层的一部分被氧化。在氮化硅层和开口中形成平面化绝缘层，例如旋涂玻璃。将绝缘层回蚀刻以露出氮化硅，其中绝缘层的上表面与导电层的上表面平齐。然后去除氮化硅层。然后在导电层上形成平面硅化物层。

17. 发明授权

US5500557A Structure and method for fabricating integrated circuits 失效
标题翻译：集成电路制造的结构和方法
公开(公告)号：US5500557A
公开(公告)日：1996-03-19
申请号：US126673
申请日：1993-09-24
申请人： Tsiu C. Chan , Frank R. Bryant , Lun-Tseng Lu , Che-Chia Wei
发明人： Tsiu C. Chan , Frank R. Bryant , Lun-Tseng Lu , Che-Chia Wei
IPC分类号： H01L23/528 , H01L23/532 , H01L23/48
CPC分类号： H01L23/5283 , H01L23/53271 , H01L2924/0002
摘要： A structure and method for fabricating integrated circuits which provides for the detection of residual conductive material. A first conductive layer is deposited over the integrated circuit and patterned to define a first interconnect layer. An insulating layer is then formed over the integrated circuit. A second conductive layer is then deposited and patterned to define a second interconnect layer. Residual conductive material can be formed during patterning of the second interconnect layer when portions of the second conductive layer remain adjacent to the vertical sidewalls of the first interconnect layer. To make the residual conductive material easier to detect, the conductivity of the residual conductive material is increased by either implanting impurities into the integrated circuit or siliciding the residual conductive material with a refractory metal.
摘要翻译：用于制造集成电路的结构和方法，其提供残留导电材料的检测。第一导电层沉积在集成电路上并被图案化以限定第一互连层。然后在集成电路上形成绝缘层。然后沉积和图案化第二导电层以限定第二互连层。当第二导电层的部分保持与第一互连层的垂直侧壁相邻时，可以在图案化第二互连层期间形成剩余的导电材料。为了使残留的导电材料更易于检测，通过将杂质注入集成电路或用难熔金属硅化残留的导电材料来增加剩余导电材料的导电性。

18. 发明授权

US5478771A Method of forming local interconnect structure without P-N junction between active elements 失效
标题翻译：在有源元件之间形成不具有P-N结的局部互连结构的方法
公开(公告)号：US5478771A
公开(公告)日：1995-12-26
申请号：US359006
申请日：1994-12-19
申请人： Tsiu C. Chan , Frank R. Bryant , John L. Walters
发明人： Tsiu C. Chan , Frank R. Bryant , John L. Walters
IPC分类号： H01L21/768 , H01L23/532 , H01L27/11 , H01L21/70
CPC分类号： H01L23/53271 , H01L21/76889 , H01L21/76895 , H01L27/1104 , H01L2924/0002 , Y10S148/039 , Y10S257/903
摘要： An interconnect structure, and method for forming same, is suitable for use in integrated circuits such as SRAM devices. The structure uses masking of a polycrystalline silicon interconnect level to move a P-N junction to a region within a polycrystalline silicon interconnect line, rather than at the substrate. This P-N junction can then be shorted out using a refractory metal silicide formed on the polycrystalline silicon interconnect structure.
摘要翻译：互连结构及其形成方法适用于诸如SRAM器件的集成电路。该结构使用多晶硅互连电平的掩模将P-N结移动到多晶硅互连线内的区域，而不是在衬底处。然后可以使用形成在多晶硅互连结构上的难熔金属硅化物来短路该P-N结。

19. 发明授权

US5231043A Contact alignment for integrated circuits 失效
标题翻译：集成电路接点对齐
公开(公告)号：US5231043A
公开(公告)日：1993-07-27
申请号：US748085
申请日：1991-08-21
申请人： Tsiu C. Chan , Frank R. Bryant
发明人： Tsiu C. Chan , Frank R. Bryant
IPC分类号： H01L21/768 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10852 , H01L21/76802 , H01L27/10805
摘要： A technique for producing self-aligned contact openings is especially useful when the openings are to be made between conductive structures having relatively small separation. Formation of an oxide layer under particular process conditions results in a thicker layer of oxide on top of the conductive structures, and a thinner oxide layer along the sidewalls and in the bottom of the spacing between them. Deposition of such a differential thickness oxide layer can be followed by an unmasked-anisotropic etch in order to clear the oxide from the space between the conductive structures, without removing all of the oxide layer over the conductive structure. Such a technique can be utilized in integrated circuits such as DRAMs, with the word lines allowing for the formation of semi-self-aligned bit lines. The combination of word lines and bit lines can provide for a fully self-aligned contact opening for DRAM cell capacitors.

20. 发明授权

US5204279A Method of making SRAM cell and structure with polycrystalline p-channel load devices 失效
标题翻译：制造具有多晶p沟道负载器件的SRAM单元和结构的方法
公开(公告)号：US5204279A
公开(公告)日：1993-04-20
申请号：US709354
申请日：1991-06-03
申请人： Tsiu C. Chan , Frank R. Bryant , Lisa K. Jorgenson
发明人： Tsiu C. Chan , Frank R. Bryant , Lisa K. Jorgenson
IPC分类号： H01L21/8244 , H01L27/11
CPC分类号： H01L27/11 , H01L27/1108 , Y10S257/903
摘要： A method for forming a SRAM structure with polycrystalline P-channel load devices of an integrated circuit, and an integrated circuit formed according to the same, is disclosed. A field oxide region is formed over a portion of the substrate. A first gate electrode of a first N-channel field effect device is formed over the substrate having a source/drain region in the substrate. A second gate electrode of a second N-channel field effect device is also formed over the substrate and a portion of the field oxide. A first insulating layer is formed over the integrated circuit containing an opening exposing a portion of the source/drain region and the second gate electrode of the first and second N-channel devices respectively. An interconnect layer having a doped polysilicon layer and a barrier layer is formed over the integrated circuit, patterned and etched to define a shared contact region covering the exposed source/drain region and the second gate electrode of the N-channel devices. A second insulating layer is formed over the integrated circuit having an opening exposing a portion of the interconnect layer. A first conductive layer is formed over the integrated circuit, patterned and etched to define a first and a second gate electrode of a first and a second P-channel field effect device respectively. A gate oxide layer is formed over a portion of the first gate electrode and a portion of the second gate electrode of the first and second P-channel devices. A second conductive layer is formed over the integrated circuit, patterned and etched to define a source/drain and channel region of the first gate electrode of the first P-channel device and covering a portion of the second gate electrode of the second P-channel device.
摘要翻译：公开了一种用于形成具有集成电路的多晶P沟道负载装置的SRAM结构的方法，以及根据该集成电路形成的集成电路。在衬底的一部分上形成场氧化物区域。在衬底上形成第一N沟道场效应器件的第一栅电极，该衬底上具有衬底中的源/漏区。第二N沟道场效应器件的第二栅电极也形成在衬底和场氧化物的一部分上。在集成电路上形成第一绝缘层，该集成电路包含分别露出第一和第二N沟道器件的源极/漏极区域和第二栅极电极的一部分的开口。在集成电路上形成具有掺杂多晶硅层和阻挡层的互连层，被图案化和蚀刻以限定覆盖N沟道器件的暴露的源极/漏极区域和第二栅极电极的共享接触区域。在集成电路上形成第二绝缘层，该绝缘层具有露出互连层的一部分的开口。在集成电路上形成第一导电层，被图案化和蚀刻以分别限定第一和第二P沟道场效应器件的第一和第二栅电极。在第一栅电极的一部分和第一和第二P沟道器件的第二栅电极的一部分上形成栅氧化层。在集成电路上形成第二导电层，被图案化和蚀刻以限定第一P沟道器件的第一栅电极的源极/漏极和沟道区，并且覆盖第二P沟道的第二栅电极的一部分设备。

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