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11. 发明授权

US07046045B2 SOI sense amplifier with cross-coupled bit line structure 有权
标题翻译：具有交叉耦合位线结构的SOI读出放大器
公开(公告)号：US07046045B2
公开(公告)日：2006-05-16
申请号：US10852889
申请日：2004-05-25
申请人： Takaaki Nakazato , Toru Asano , Osamu Takahashi , Sang Dhong
发明人： Takaaki Nakazato , Toru Asano , Osamu Takahashi , Sang Dhong
IPC分类号： G01R19/00 , G11C7/00 , H03F3/45
CPC分类号： H03F3/45188
摘要： Systems and methods for decreasing the sensitivity of a sense amplifier to variations in the threshold voltages of the data line pull-down transistors by pre-charging the intermediate nodes of the sense amplifier to the voltages on the opposing bit lines when the sense amplifier is not enabled. In one embodiment, the intermediate nodes are coupled to the input bit lines through transistors that are switched on when the sense amplifier is not enabled and switched off when the sense amplifier is enabled. In one embodiment, the intermediate nodes are pre-charged to a predetermined voltage before being pre-charged to the voltages on the bit lines. In one embodiment, the bodies of the data line pull-down transistors may also be body-tied to the opposing intermediate nodes to increase current flow through these transistors, particularly on the side of the sense amplifier that will be pulled low when the sense amplifier is enabled.
摘要翻译：当读出放大器不是时，将读出放大器的中间节点预充电到相对位线上的电压，从而降低读出放大器对数据线下拉晶体管阈值电压变化的灵敏度的系统和方法启用在一个实施例中，中间节点通过晶体管耦合到输入位线，晶体管在读出放大器未使能时被接通，当读出放大器被使能时，它们被关断。在一个实施例中，中间节点在被预充电到位线上的电压之前被预充电到预定电压。在一个实施例中，数据线下拉晶体管的主体也可以被机构连接到相对的中间节点，以增加通过这些晶体管的电流，特别是在读出放大器的一侧，当读出放大器启用。

12. 发明申请

US20060098520A1 Apparatus and method of word line decoding for deep pipelined memory 失效
标题翻译：深层流水线存储器的字线解码装置及方法
公开(公告)号：US20060098520A1
公开(公告)日：2006-05-11
申请号：US10982109
申请日：2004-11-05
申请人： Toru Asano , Sang Dhong , Takaaki Nakazato , Osamu Takahashi
发明人： Toru Asano , Sang Dhong , Takaaki Nakazato , Osamu Takahashi
IPC分类号： G11C8/00 , G11C7/10
CPC分类号： G11C7/1039 , G11C8/08 , G11C8/10
摘要： A method, an apparatus, and a computer program are provided to reduce the number of required latches in a deep pipeline wordline (WL) decoder. Traditionally, a signal local clock buffer (LCB) has been responsible for providing a driving signal to a WL driver. However, with this configuration, a large number of latches are utilized. To reduce this latch usage, a number of LCBs are employed, such that one latch can enable an increased number of WLs. Hence, the overall area occupied by latches is reduced and power consumption is reduced.
摘要翻译：提供了一种方法，装置和计算机程序以减少深流水线字线（WL）解码器中所需的锁存器的数量。传统上，信号本地时钟缓冲器（LCB）已经负责向WL驱动器提供驱动信号。然而，利用该配置，使用大量的锁存器。为了减少该锁存器的使用，采用多个LCB，使得一个锁存器能够增加数量的WL。因此，锁存器占用的总体面积减少，功耗降低。

13. 发明申请

US20050264323A1 SOI sense amplifier with cross-coupled bit line structure 有权
标题翻译：具有交叉耦合位线结构的SOI读出放大器
公开(公告)号：US20050264323A1
公开(公告)日：2005-12-01
申请号：US10852889
申请日：2004-05-25
申请人： Takaaki Nakazato , Toru Asano , Osamu Takahashi , Sang Dhong
发明人： Takaaki Nakazato , Toru Asano , Osamu Takahashi , Sang Dhong
IPC分类号： G11C11/419 , H03F3/45
CPC分类号： H03F3/45188
摘要： Systems and methods for decreasing the sensitivity of a sense amplifier to variations in the threshold voltages of the data line pull-down transistors by pre-charging the intermediate nodes of the sense amplifier to the voltages on the opposing bit lines when the sense amplifier is not enabled. In one embodiment, the intermediate nodes are coupled to the input bit lines through transistors that are switched on when the sense amplifier is not enabled and switched off when the sense amplifier is enabled. In one embodiment, the intermediate nodes are pre-charged to a predetermined voltage before being pre-charged to the voltages on the bit lines. In one embodiment, the bodies of the data line pull-down transistors may also be body-tied to the opposing intermediate nodes to increase current flow through these transistors, particularly on the side of the sense amplifier that will be pulled low when the sense amplifier is enabled.
摘要翻译：当读出放大器不是时，将读出放大器的中间节点预充电到相对位线上的电压，从而降低读出放大器对数据线下拉晶体管阈值电压变化的灵敏度的系统和方法启用在一个实施例中，中间节点通过晶体管耦合到输入位线，晶体管在读出放大器未使能时被接通，当读出放大器被使能时，它们被关断。在一个实施例中，中间节点在被预充电到位线上的电压之前被预充电到预定电压。在一个实施例中，数据线下拉晶体管的主体也可以被机构连接到相对的中间节点，以增加通过这些晶体管的电流，特别是在读出放大器的一侧，当读出放大器启用。

14. 发明授权

US06850456B2 Subarray control and subarray cell access in a memory module 失效
标题翻译：存储器模块中的子阵列控制和子阵列单元访问
公开(公告)号：US06850456B2
公开(公告)日：2005-02-01
申请号：US10606585
申请日：2003-06-26
申请人： Toru Asano , Sang Hoo Dhong , Takaaki Nakazato , Osamu Takahashi
发明人： Toru Asano , Sang Hoo Dhong , Takaaki Nakazato , Osamu Takahashi
IPC分类号： G11C7/22 , G11C8/08 , G11C8/18 , G11C8/00
CPC分类号： G11C7/22 , G11C8/08 , G11C8/18
摘要： The present invention provides a subarray control apparatus and method. The subarray control includes a wordline driver configured to generate a wordline activation signal, and a write/read control signal generator configured to generate a write/read enable signal. In addition, the subarray control includes a timing generator configured to generate a wordline timing signal input to the wordline driver and a write/read timing signal input to the write/read control signal generator. The wordline activation signal is based on enable data captured by a first transparent latching circuit and the wordline timing signal generated within the subarray. The write/read enable signal is based on enable data captured by a second transparent latching circuit and the write/read timing signal generated within the subarray. Accessing subarray cells in a memory module and a memory module incorporating the subarray control are also disclosed.
摘要翻译：本发明提供了一种子阵列控制装置和方法。子阵列控制包括被配置为产生字线激活信号的字线驱动器，以及被配置为产生写/读使能信号的写/读控制信号发生器。此外，子阵列控制包括定时发生器，其被配置为产生输入到字线驱动器的字线定时信号和输入到写/读控制信号发生器的写/读定时信号。字线激活信号基于由第一透明锁存电路捕获的使能数据和在子阵列内生成的字线定时信号。写/读使能信号基于由第二透明锁存电路捕获的使能数据和在子阵列内生成的写/读定时信号。还公开了存储器模块中的子阵列单元和并入子阵列控制的存储器模块。

15. 发明授权

US07444525B2 Methods and apparatus for reducing leakage current in a disabled SOI circuit 有权
标题翻译：用于减少残留SOI电路中漏电流的方法和装置
公开(公告)号：US07444525B2
公开(公告)日：2008-10-28
申请号：US11137234
申请日：2005-05-25
申请人： Hiroshi Yoshihara , Sang Hoo Dhong , Osamu Takahashi , Takaaki Nakazato
发明人： Hiroshi Yoshihara , Sang Hoo Dhong , Osamu Takahashi , Takaaki Nakazato
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： H03K19/0016
摘要： Methods and apparatus provide for enabling a digital circuit by biasing at least one switch transistor ON such that a voltage potential of a virtual ground node is substantially equal to a voltage potential of a ground node for a power supply to the digital circuit, wherein the digital circuit is implemented using a plurality of transistors in a silicon-on-insulator (SOI) arrangement and at least some of the transistors are referenced to the virtual ground node; and disabling the digital circuit by biasing a gate terminal of the switch transistor below the voltage potential of the ground node.
摘要翻译：方法和装置提供了通过使至少一个开关晶体管导通来使能数字电路，使得虚拟接地节点的电压电位基本上等于用于数字电路的电源的接地节点的电压电位，其中数字电路使用绝缘体上硅（SOI）布置中的多个晶体管实现，并且至少一些晶体管参考虚拟接地节点; 以及通过将所述开关晶体管的栅极端子偏压到所述接地节点的电压电位以下来禁止所述数字电路。

16. 发明申请

US20060270173A1 Methods and apparatus for reducing leakage current in a disabled SOI circuit 有权
标题翻译：用于减少残留SOI电路中漏电流的方法和装置
公开(公告)号：US20060270173A1
公开(公告)日：2006-11-30
申请号：US11137234
申请日：2005-05-25
申请人： Hiroshi Yoshihara , Sang Dhong , Osamu Takahashi , Takaaki Nakazato
发明人： Hiroshi Yoshihara , Sang Dhong , Osamu Takahashi , Takaaki Nakazato
IPC分类号： G06F1/00 , H01L21/8222 , H01L27/12
CPC分类号： H03K19/0016
摘要： Methods and apparatus provide for enabling a digital circuit by biasing at least one switch transistor ON such that a voltage potential of a virtual ground node is substantially equal to a voltage potential of a ground node for a power supply to the digital circuit, wherein the digital circuit is implemented using a plurality of transistors in a silicon-on-insulator (SOI) arrangement and at least some of the transistors are referenced to the virtual ground node; and disabling the digital circuit by biasing a gate terminal of the switch transistor below the voltage potential of the ground node.
摘要翻译：方法和装置提供了通过使至少一个开关晶体管导通来使能数字电路，使得虚拟接地节点的电压电位基本上等于用于数字电路的电源的接地节点的电压电位，其中数字电路使用绝缘体上硅（SOI）布置中的多个晶体管实现，并且至少一些晶体管参考虚拟接地节点; 以及通过将所述开关晶体管的栅极端子偏压到所述接地节点的电压电位以下来禁止所述数字电路。

17. 发明授权

US06567326B2 Semiconductor memory device 失效
公开(公告)号：US06567326B2
公开(公告)日：2003-05-20
申请号：US09923948
申请日：2001-08-08
申请人： Takaaki Nakazato , Yukihiro Fujimoto
发明人： Takaaki Nakazato , Yukihiro Fujimoto
IPC分类号： G11C700
CPC分类号： G11C7/1012 , G11C7/065 , G11C7/1051 , G11C11/4093 , G11C11/419
摘要： A semiconductor device comprises a first bit line, a second bit line, a memory cell electrically coupled to the first bit line and the second bit line, a first amplification circuit configured to amplify a potential of the first bit line and a second amplification circuit configured to amplify a potential of the second bit line.

18. 发明授权

US07719880B2 Method and system for semiconductor memory 失效
标题翻译：半导体存储器的方法和系统
公开(公告)号：US07719880B2
公开(公告)日：2010-05-18
申请号：US12029731
申请日：2008-02-12
申请人： Takaaki Nakazato
发明人： Takaaki Nakazato
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , H01L27/1104
摘要： Methods and systems for embodiments of a 9T memory cell, memory devices which utilize such 9T memory cells and the creation of embodiments of such memory devices are disclosed. More specifically, an embodiment of a 9T memory cell may comprise a 6T memory cell portion and a 3T read port. Additionally, in one embodiment, a memory which utilizes 9T memory cells may be made by from a grid comprising columns and rows of transistors formed according to a layout for 6T memory cells.
摘要翻译：公开了用于9T存储器单元的实施例的方法和系统，利用这种9T存储器单元的存储器件以及这种存储器件的实施例的创建。更具体地，9T存储单元的实施例可以包括6T存储器单元部分和3T读取端口。另外，在一个实施例中，利用9T存储单元的存储器可以由包括根据6T存储器单元的布局形成的晶体管列和行的栅格制成。

19. 发明申请

US20060012403A1 Systems and methods for controlling timing in a circuit 失效
标题翻译：控制电路定时的系统和方法
公开(公告)号：US20060012403A1
公开(公告)日：2006-01-19
申请号：US10890084
申请日：2004-07-13
申请人： Atsushi Kawasumi , Takaaki Nakazato
发明人： Atsushi Kawasumi , Takaaki Nakazato
IPC分类号： G01R19/00
CPC分类号： G11C7/08
摘要： Systems and methods for reducing or eliminating the effect of timing variations in signals generated by devices that are subject to the history effect, wherein devices are enabled using a combination of timing signals, some of which are subject to timing variations arising from the history effect, and some of which are not. In one embodiment, a sense amplifier includes a pair of serially configured transistors that couple the sense amplifier to ground. One of the transistors is switched on/off by a clock signal that is not subject to history-effect timing variations, and the other is switched on/off by a signal that is subject to such variations. The second signal has pulses that are selectively delayed so that they will (or will not) overlap with the pulses of the clock signal in a controlled manner.
摘要翻译：用于减少或消除由经历历史效应的设备产生的信号中的定时变化的影响的系统和方法，其中使用定时信号的组合启用设备，其中一些定时信号中的一些受历史效应引起的定时变化，其中一些不是。在一个实施例中，读出放大器包括将感测放大器耦合到地的一对串联配置的晶体管。其中一个晶体管由不受历史效应定时变化影响的时钟信号导通/截止，另一个由受到这种变化的信号导通/关断。第二信号具有选择性延迟的脉冲，使得它们（或将不会）以受控的方式与时钟信号的脉冲重叠。

20. 发明申请

US20090201719A1 Method and System for Semiconductor Memory 失效
标题翻译：半导体存储器的方法和系统
公开(公告)号：US20090201719A1
公开(公告)日：2009-08-13
申请号：US12029731
申请日：2008-02-12
申请人： Takaaki Nakazato
发明人： Takaaki Nakazato
IPC分类号： G11C11/00 , H01L21/336
CPC分类号： G11C11/412 , H01L27/1104
摘要： Methods and systems for embodiments of a 9T memory cell, memory devices which utilize such 9T memory cells and the creation of embodiments of such memory devices are disclosed. More specifically, an embodiment of a 9T memory cell may comprise a 6T memory cell portion and a 3T read port. Additionally, in one embodiment, a memory which utilizes 9T memory cells may be made by from a grid comprising columns and rows of transistors formed according to a layout for 6T memory cells.
摘要翻译：公开了用于9T存储器单元的实施例的方法和系统，利用这种9T存储器单元的存储器件以及这种存储器件的实施例的创建。更具体地，9T存储单元的实施例可以包括6T存储器单元部分和3T读取端口。另外，在一个实施例中，利用9T存储单元的存储器可以由包括根据6T存储器单元的布局形成的晶体管列和行的栅格制成。

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