会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 11. 发明授权
    • Compiler for optimization in generating instruction sequence and
compiling method
    • 编译器,用于优化生成指令序列和编译方法
    • US6113650A
    • 2000-09-05
    • US108387
    • 1998-07-01
    • Junji Sakai
    • Junji Sakai
    • G06F15/16G06F9/45G06F15/80
    • G06F8/4442G06F8/452
    • A compiler has optimization processing part which comprise a loop normalization processing part for normalizing a loop structure in an intermediate language program, a subscript expression analyzing part for analyzing the presence or not of non-aligned access in the normalized loop structure, an SIMD instruction converting part for modifying an intermediate code so to perform computing of the array elements by using an SIMD instruction sequence, and a non-aligned access processing part for recognizing parts which are not word-aligned access in the array elements on a main storage subjected to the SIMD computing and converting a part of the non-aligned access into a combination of wored-aligned access instructions and shift instructions with logical instructions.
    • 编译器具有优化处理部分,其包括用于对中间语言程序中的循环结构进行归一化的循环归一化处理部分,用于分析归一化循环结构中不对准访问的存在与否的下标表达分析部分,SIMD指令转换 用于修改中间代码的部分,以便通过使用SIMD指令序列来执行阵列元素的计算;以及非对齐访问处理部分,用于识别经受所述主体存储器的主存储器上的数组元素中不是字对齐访问的部分 SIMD计算并将一部分非对准访问转换为具有逻辑指令的错位对齐访问指令和移位指令的组合。
    • 13. 发明授权
    • Schedule decision device, parallel execution device, schedule decision method, and program
    • 计划决策装置,并行执行装置,进度决策方法和程序
    • US08881158B2
    • 2014-11-04
    • US13063232
    • 2009-08-20
    • Noriaki SuzukiJunji Sakai
    • Noriaki SuzukiJunji Sakai
    • G06F9/46G06F9/50
    • G06F9/5038G06F2209/5017G06F2209/506
    • A schedule decision method acquires dependencies of execution sequences required for a plurality of sub tasks into which a first task has been divided; generates a plurality of sub task structure candidates that satisfy said dependencies and for which a plurality of processing devices execute said plurality of sub tasks; generates a plurality of schedule candidates by further assigning at least one second task to each of said sub task structure candidates; computes an effective degree that represents effectiveness of executions of said first task and said second task for each of said plurality of schedule candidates; and decides a schedule candidate used for the executions of said first task and said second task from said plurality of schedule candidates based on said effective degrees.
    • 时间表决定方法获取第一任务被划分到的多个子任务所需的执行序列的依赖关系; 生成满足所述依赖性的多个子任务结构候选,并且多个处理装置执行所述多个子任务; 通过对每个所述子任务结构候选进一步分配至少一个第二任务来生成多个调度候选; 计算表示对于所述多个日程表候选中的每一个的所述第一任务和所述第二任务的执行的有效性的有效程度; 并且基于所述有效度,从所述多个日程表候选中确定用于执行所述第一任务和所述第二任务的日程表候选。
    • 14. 发明授权
    • Trace/failure observation system, trace/failure observation method, and trace/failure observation program
    • 跟踪/故障观察系统,跟踪/故障观察方法和跟踪/故障观察程序
    • US08799753B2
    • 2014-08-05
    • US12863934
    • 2009-02-03
    • Noriaki SuzukiJunji Sakai
    • Noriaki SuzukiJunji Sakai
    • G06F7/02G06F11/00G06F11/36
    • G06F11/3636G06F11/3648
    • There is provided a trace/failure observation system which is capable of comprehensive collection of information that is needed for checking a desired operation in a system or the like where the amount of information to be observed is large, and which allows easy analysis of the desired operation. The system includes, in a system LSI to be subjected to trace/failure observation: an event detecting means for observing behavior of a portion to be observed; a first data reducing means for performing observation data reduction processing so that observation data from the event detecting means has an amount of information processable to a second data reducing means; and the second data reducing means for performing one or more steps of observation data reduction processing.
    • 提供了一种跟踪/故障观察系统,其能够综合地收集在要观察的信息量大的系统等中检查所需操作所需的信息,并且允许容易地分析所需的 操作。 该系统包括在要进行跟踪/故障观察的系统LSI中:事件检测装置,用于观察待观察部分的行为; 第一数据减少装置,用于执行观察数据缩减处理,使得来自事件检测装置的观察数据具有可处理到第二数据减少装置的信息量; 以及用于执行观察数据缩减处理的一个或多个步骤的第二数据减少装置。
    • 15. 发明申请
    • MULTIPLE PROCESSOR SYSTEM, SYSTEM STRUCTURING METHOD IN MULTIPLE PROCESSOR SYSTEM AND PROGRAM THEREOF
    • 多处理器系统中的多处理器系统,系统结构方法及其程序
    • US20100100706A1
    • 2010-04-22
    • US12447513
    • 2007-11-01
    • Hiroaki InoueJunji SakaiTsuyoshi AbeMasato Edahiro
    • Hiroaki InoueJunji SakaiTsuyoshi AbeMasato Edahiro
    • G06F15/80
    • G06F9/5077G06F9/4405H04L29/08144H04L67/34
    • For flexibly setting up an execution environment according to contents of processing to be executed while taking stability or a security level into consideration, the multiple processor system includes the execution environment main control unit 10 which determines CPU assignment at the time of deciding CPU assignment, the execution environment sub control unit 20 which controls starting, stopping and switching of an execution environment according to an instruction from the execution environment main control unit 10 to synchronize with the execution environment main control unit 10, and the execution environment management unit 30 which receives input of management information or reference refusal information of shared resources for each CPU 4 or each execution environment 100 to separate the execution environment main control unit 10 from the execution environment sub control units 20a through 20n, or the execution environment sub control units 20aA through 20n from each other.
    • 为了在考虑到稳定性或安全级别的同时根据要执行的处理的内容灵活地设置执行环境,多处理器系统包括确定CPU分配时的CPU分配的执行环境主控制单元10, 执行环境子控制单元20,其根据来自执行环境主控制单元10的指令控制执行环境的启动,停止和切换,以与执行环境主控制单元10同步;以及执行环境管理单元30,其接收输入 对于每个CPU 4或每个执行环境100的共享资源的管理信息或参考拒绝信息,以将执行环境主控制单元10与执行环境子控制单元20a至20n或执行环境子控制单元20aA至20n分离 彼此。
    • 18. 发明授权
    • Performance optimization system, method and program
    • 性能优化系统,方法和程序
    • US08738881B2
    • 2014-05-27
    • US12865781
    • 2009-02-06
    • Noriaki SuzukiSunao ToriiJunji Sakai
    • Noriaki SuzukiSunao ToriiJunji Sakai
    • G06F12/08G06F3/06
    • G06F3/0644G06F11/3419G06F11/3466G06F12/0802G06F2201/88G06F2201/885
    • Provided is a performance optimization system that can identify a case where the impact on performance is large even when the number of cache misses is small. The performance optimization system includes: a required-period-of-time measurement unit that measures a required period of time concerning a to-be-observed access; a required-period-of-time table holding unit that holds a required-period-of-time table that consists of a plurality of table entries in which stored are measured values of the required period of time for each of classification regions produced by dividing a memory region for each of types based on the to-be-observed access to store a measured value of the required period of time; a table entry selection unit that makes a selection as to in which table entry, out of a plurality of table entries for each of the classification regions that make up the required-period-of-time table, the measured value of the required period of time is stored on the basis of the to-be-observed access; and a cache miss observation unit that detects the occurrence of a cache miss associated with the to-be-observed access.
    • 提供了一种性能优化系统,可以识别即使高速缓存未命中的数量较小,对性能的影响也很大的情况。 绩效优化系统包括:一个需要的时间测量单元,用于测量与待观察的访问有关的所需时间; 所需时间表保持单元,其保存由存储的多个表条目组成的所需时间周期表,所述时间表存储的是通过划分产生的每个分类区域所需的时间段的测量值 基于待观察访问的每种类型的存储区域来存储所需时间段的测量值; 表格条目选择单元,对于构成所需时间表的每个分类区域的多个表条目中的哪个表条目进行选择所需时间段的测量值 时间根据被观察的访问存储; 以及高速缓存未命中观察单元,其检测与所述待观察访问相关联的高速缓存未命中的发生。
    • 19. 发明授权
    • Information processing apparatus, execution environment transferring method and program thereof
    • 信息处理装置,执行环境转移方法及程序
    • US08473702B2
    • 2013-06-25
    • US12602871
    • 2008-06-05
    • Hiroaki InoueTsuyoshi AbeJunji SakaiMasato Edahiro
    • Hiroaki InoueTsuyoshi AbeJunji SakaiMasato Edahiro
    • G06F12/00
    • G06F9/44505G06F9/4856
    • Provided is an information processing device which enables transfer of an execution environment in a short time period without degrading basic performance of an execution environment and without requiring a large amount of memory.The information processing device comprises a basic side CPU 100 for executing basic processing and an addition side CPU 200 for executing additional processing, in which a transfer management unit 300 provided on the basic side CPU 100 transfers execution environment data 1000 including constitution information of an execution environment 30 of the additional processing to be executed on the addition side CPU and data in a memory corresponding to the execution environment to other information processing device and restores the execution environment to re-start the addition side CPU based on the received execution environment data 1000.
    • 提供一种能够在短时间内传送执行环境而不降低执行环境的基本性能而不需要大量存储器的信息处理装置。 信息处理装置包括用于执行基本处理的基本侧CPU 100和用于执行附加处理的附加侧CPU200,其中设置在基本侧CPU 100上的传送管理单元300传送包括执行的结构信息的执行环境数据1000 在附加侧CPU执行的附加处理的环境30和与执行环境相对应的存储器中的数据到其他信息处理装置,并且基于接收到的执行环境数据1000恢复执行环境以重新启动加法侧CPU 。
    • 20. 发明申请
    • PROGRAM PARALLELIZATION APPARATUS, PROGRAM PARALLELIZATION METHOD, AND PROGRAM PARALLELIZATION PROGRAM
    • 程序并行化设备,程序并行化方案和程序并行程序
    • US20110067015A1
    • 2011-03-17
    • US12866219
    • 2009-02-12
    • Masamichi TakagiJunji Sakai
    • Masamichi TakagiJunji Sakai
    • G06F9/45
    • G06F8/456
    • A program parallelization apparatus which generates a parallelized program of shorter parallel execution time is provided. The program parallelization apparatus inputs a sequential processing intermediate program and outputs a parallelized intermediate program. In the apparatus, a thread start time limitation analysis part analyzes an instruction-allocatable time based on a limitation on an instruction execution start time of each thread. A thread end time limitation analysis part analyzes an instruction-allocatable time based on a limitation on an instruction execution end time of each thread. An occupancy status analysis part analyzes a time not occupied by already-scheduled instructions. A dependence delay analysis part analyzes an instruction-allocatable time based on a delay resulting from dependence between instructions. A schedule candidate instruction select part selects a next instruction to schedule. An instruction arrangement part allocates a processor and time to execute to an instruction.
    • 提供了一种生成并行执行时间较短并行程序的程序并行化装置。 程序并行化装置输入顺序处理中间程序并输出并行化的中间程序。 在该装置中,线程开始时间限制分析部分基于对每个线程的指令执行开始时间的限制来分析指令可分配时间。 线程结束时间限制分析部分基于对每个线程的指令执行结束时间的限制来分析指令可分配时间。 占用状态分析部分分析未被计划的指令占用的时间。 依赖延迟分析部分基于由指令之间的依赖导致的延迟来分析指令可分配时间。 时间表候选指令选择部分选择要调度的下一个指令。 指令排列部分分配处理器和执行指令的时间。