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11. 发明授权

US07117398B2 Program counter range comparator with equality, greater than, less than and non-equal detection modes 有权
公开(公告)号：US07117398B2
公开(公告)日：2006-10-03
申请号：US10302192
申请日：2002-11-22
申请人： Jose L. Flores , Lewis Nardini , Maria B. H. Gill
发明人： Jose L. Flores , Lewis Nardini , Maria B. H. Gill
IPC分类号： G06F11/30 , G06F7/02
CPC分类号： G06F11/3636 , G06F11/3656
摘要： An program counter address comparator includes two comparators comparing an input program counter address with respective reference addresses. The comparators produce a match indication on selectable criteria, such as greater than, less than, equal to, not equal to, less than or equal to, and greater than or equal to, and can be selectively chained. Input multiplexers permit selection of either the program counter address bus or a secondary address bus. The reference addresses and control functions are enabled via central processing unit accessible memory mapped registers.

12. 发明授权

US07051197B2 Tracing through reset 有权
标题翻译：跟踪通过重置
公开(公告)号：US07051197B2
公开(公告)日：2006-05-23
申请号：US10302082
申请日：2002-11-22
申请人： Manisha Agarwala , Lewis Nardini
发明人： Manisha Agarwala , Lewis Nardini
IPC分类号： G06F11/00
CPC分类号： G06F11/3636 , G06F11/3656
摘要： A method of tracing a data processor upon reset of the data processor. A data processor reset signal resets the data processor, part of trace collection hardware and does not reset remaining parts of trace collection hardware. The data processor reset signal may be not owned, owned by an application program or owned by a debugger. The partial not reset of the trace collection hardware occurs only upon a data processor reset signal owned by the debugger. A trace logic reset signal resets both the data processor and the trace collection hardware when not owned. This trace logic reset signal resets the data processor only when owned by the debugger and resets the trace collection hardware when owned by an application program.
摘要翻译：一种在数据处理器复位时跟踪数据处理器的方法。数据处理器复位信号复位数据处理器，跟踪收集硬件的一部分，不会复位跟踪收集硬件的剩余部分。数据处理器复位信号可以不是由应用程序所拥有或由调试器拥有的。跟踪收集硬件的部分不复位仅在调试器所拥有的数据处理器复位信号时发生。跟踪逻辑复位信号在不拥有时复位数据处理器和跟踪收集硬件。该跟踪逻辑复位信号仅在调试器拥有时复位数据处理器，并在应用程序拥有时重置跟踪收集硬件。

13. 发明授权

US07774758B2 Systems and methods for secure debugging and profiling of a computer system 有权
标题翻译：用于计算机系统安全调试和分析的系统和方法
公开(公告)号：US07774758B2
公开(公告)日：2010-08-10
申请号：US11383467
申请日：2006-05-15
申请人： Lewis Nardini , Manisha Agarwala , Oliver P. Sohm
发明人： Lewis Nardini , Manisha Agarwala , Oliver P. Sohm
IPC分类号： G06F9/44
CPC分类号： G06F11/3656 , G06F12/0897
摘要： The present disclosure describes methods and systems for secure debugging and profiling of a computer system. Some illustrative embodiments may include a system including a processor with a first processing stage and a first attribute register associated with the first processing stage, and including a memory system coupled to the processor. An instruction and an attribute value are stored within the memory system, wherein the instruction is loaded into the first processing stage and the attribute value is loaded into the first attribute register. Export of debug and profiling data from the first processing stage is disabled if the attribute value in the first attribute register indicates that the instruction in the first processing stage is a secure instruction, and further indicates that secure emulation is disabled.
摘要翻译：本公开描述了用于安全调试和分析计算机系统的方法和系统。一些说明性实施例可以包括包括具有第一处理级的处理器和与第一处理级相关联的第一属性寄存器的系统的系统，并且包括耦合到处理器的存储器系统。指令和属性值被存储在存储器系统内，其中指令被加载到第一处理级，并且属性值被加载到第一属性寄存器中。如果第一属性寄存器中的属性值指示第一处理阶段中的指令是安全指令，并且进一步指示安全仿真被禁用，则禁止从第一处理阶段导出调试和分析数据。

14. 发明授权

US07444504B2 Tracing through reset 有权
标题翻译：跟踪通过重置
公开(公告)号：US07444504B2
公开(公告)日：2008-10-28
申请号：US11820546
申请日：2007-06-20
申请人： Manisha Agarwala , Lewis Nardini
发明人： Manisha Agarwala , Lewis Nardini
IPC分类号： G06F11/00
CPC分类号： G06F11/3636 , G06F11/3656
摘要： A method of tracing a data processor upon reset of the data processor. A data processor reset signal resets the data processor, part of trace collection hardware and does not reset remaining parts of trace collection hardware. The data processor reset signal may be not owned, owned by an application program or owned by a debugger. The partial not reset of the trace collection hardware occurs only upon a data processor reset signal owned by the debugger. A trace logic reset signal resets both the data processor and the trace collection hardware when not owned. This trace logic reset signal resets the data processor only when owned by the debugger and resets the trace collection hardware when owned by an application program.
摘要翻译：一种在数据处理器复位时跟踪数据处理器的方法。数据处理器复位信号复位数据处理器，跟踪收集硬件的一部分，不会复位跟踪收集硬件的剩余部分。数据处理器复位信号可以不是由应用程序所拥有或由调试器拥有的。跟踪收集硬件的部分不复位仅在调试器所拥有的数据处理器复位信号时发生。跟踪逻辑复位信号在不拥有时复位数据处理器和跟踪收集硬件。该跟踪逻辑复位信号仅在调试器拥有时复位数据处理器，并在应用程序拥有时重置跟踪收集硬件。

15. 发明申请

US20080126871A1 Token-Based Trace System 有权
标题翻译：基于令牌的跟踪系统
公开(公告)号：US20080126871A1
公开(公告)日：2008-05-29
申请号：US11468114
申请日：2006-08-29
申请人： Lewis Nardini , Manisha Agarwala , Neil Common
发明人： Lewis Nardini , Manisha Agarwala , Neil Common
IPC分类号： G06F11/36
CPC分类号： G06F11/3636 , G06F11/3648
摘要： A system comprising a target hardware comprising multiple processor cores and an application. The system also comprises a host computer coupled to the target hardware by way of a connection and adapted to debug the application by receiving trace information via the connection. In determining which trace information to send via the connection, the target hardware gives priority to trace information generated by a primary processor core associated with a token over trace information generated by a secondary processor core not associated with the token. The token is associated with one of the multiple processor cores at a time.
摘要翻译：一种包括包括多个处理器核心和应用的目标硬件的系统。该系统还包括通过连接耦合到目标硬件的主计算机，并适于通过经由连接接收跟踪信息来调试应用程序。在确定通过连接发送的跟踪信息时，目标硬件优先于由与令牌相关联的主处理器核心生成的跟踪信息优先于由与令牌不相关联的辅助处理器核心生成的跟踪信息。令牌每次与多个处理器内核之一相关联。

16. 发明申请

US20070094537A1 Address Range Comparator for Detection of Multi-Size Memory Accesses With Data Matching Qualification and Full or Partial Overlap 有权
标题翻译：用于通过数据匹配鉴定和全部或部分重叠检测多尺寸存储器访问的地址范围比较器
公开(公告)号：US20070094537A1
公开(公告)日：2007-04-26
申请号：US11566772
申请日：2006-12-05
申请人： Jose Flores , Lewis Nardini , Maria Gill
发明人： Jose Flores , Lewis Nardini , Maria Gill
IPC分类号： G06F11/00
CPC分类号： G06F11/3648 , G01R31/31703 , G01R31/31705 , G06F11/3656
摘要： An memory access address comparator includes two comparators comparing an input memory access address with respective reference addresses. The comparators produce a match indication on selectable criteria, such as address size, full or partial overlap, greater than, less than, equal to, not equal to, less than or equal to, and greater than or equal to, and can be selectively chained. Input multiplexers permit memory access address bus selection. The comparator output may be selectively dependent upon corresponding data matches. The reference addresses, comparison data and control functions are enabled via central processing unit accessible memory mapped registers.
摘要翻译：存储器访问地址比较器包括将输入存储器访问地址与相应的参考地址进行比较的两个比较器。比较器根据可选择的标准产生匹配指示，例如地址大小，全部或部分重叠，大于，小于，等于，不等于，小于等于并且大于或等于，并且可以是选择性地链接。输入多路复用器允许存储器访问地址总线选择。比较器输出可以选择性地依赖于相应的数据匹配。参考地址，比较数据和控制功能通过中央处理单元可访问存储器映射寄存器使能。

17. 发明授权

US06996735B2 Apparatus for alignment of data collected from multiple pipe stages with heterogeneous retention policies in an unprotected pipeline 有权
标题翻译：用于将从多个管道段收集的数据与不受保护管道中的异质保留策略对齐的装置
公开(公告)号：US06996735B2
公开(公告)日：2006-02-07
申请号：US10302236
申请日：2002-11-22
申请人： Jose L. Flores , Lewis Nardini
发明人： Jose L. Flores , Lewis Nardini
IPC分类号： G06F1/12
CPC分类号： G06F9/3869 , G06F9/321
摘要： A method and apparatus for trace data alignment for trace data generated during differing instruction pipeline stages selectively delays write data, memory access address and memory access control data zero, one or two pipeline stages dependent upon the memory access control data. Program counter data delayed by one clock cycle is delayed one pipeline stage if the next instruction is a new instruction. Program counter control data is also delayed one pipeline stage. The write data, memory access address, memory access control data, program counter data and program counter control data are further delayed a number of pipeline stages to align with read data. The program counter data holds if the pipeline is stalled. The write data, memory access address, memory access control data, program counter data and program counter control data holds in the multistage pipeline delay register if the pipeline is stalled.
摘要翻译：用于在不同指令流水线阶段期间生成的跟踪数据的跟踪数据对准的方法和装置有选择地将写入数据，存储器访问地址和存储器访问控制数据零延迟，取决于存储器访问控制数据的一个或两个流水线级。如果下一条指令是新指令，延迟一个时钟周期的程序计数器数据被延迟一个流水线级。程序计数器控制数据也在一个流水线阶段被延迟。写入数据，存储器访问地址，存储器访问控制数据，程序计数器数据和程序计数器控制数据进一步延迟了多个流水线级以与读取数据对准。如果管道停滞，则程序计数器数据保持。如果管道停滞，写入数据，存储器访问地址，存储器访问控制数据，程序计数器数据和程序计数器控制数据保持在多级流水线延迟寄存器中。

18. 发明授权

US06981178B2 Separation of debug windows by IDS bit 有权
标题翻译：通过IDS位分离调试窗口
公开(公告)号：US06981178B2
公开(公告)日：2005-12-27
申请号：US10302449
申请日：2002-11-22
申请人： Lewis Nardini , Gary L. Swoboda , Timothy D. Anderson
发明人： Lewis Nardini , Gary L. Swoboda , Timothy D. Anderson
IPC分类号： G06F11/00 , H04L1/22
CPC分类号： G06F11/3648 , G06F11/3656
摘要： A central processing unit that enables real time interrupts during a debug halt stores an interrupt during debug bit corresponding to the return address upon detection of an interrupt. The interrupt during debug bit has a first digital state if the central processing unit is in a debug halt state and a second digital state if the central processing unit is not in a debug halt state. Upon return from an interrupt the central processing unit enter a debug halt state if the interrupt during debug bit has the first state. The return address and the interrupt during debug bit can be embodied in a push-pop stack. The interrupt during debug bit register can be an unused least significant bit of the return address.
摘要翻译：在调试停止期间使能实时中断的中央处理单元在检测到中断时存储与返回地址相对应的调试期间的中断。如果中央处理单元处于调试停止状态，并且如果中央处理单元未处于调试停止状态，则调试位期间的中断具有第一数字状态。如果调试位中的中断处于第一状态，则从中断返回时，中央处理单元进入调试停止状态。调试位中的返回地址和中断可以体现在一个推挽栈中。调试位寄存器中的中断可能是返回地址的未使用的最低有效位。

19. 发明授权

US06889311B2 Pipeline stage single cycle sliding alignment correction of memory read data with integrated data reordering for load and store instructions 有权
标题翻译：流水线单周期滑动对准校正存储器读取数据，集成数据重新排序用于加载和存储指令
公开(公告)号：US06889311B2
公开(公告)日：2005-05-03
申请号：US10302084
申请日：2002-11-22
申请人： Jose L. Flores , Lewis Nardini
发明人： Jose L. Flores , Lewis Nardini
IPC分类号： G06F9/38 , G06F11/36 , G06F9/00
CPC分类号： G06F9/3863 , G06F9/3867 , G06F11/3636
摘要： Trace data is aligned in a processor having an instruction pipeline by delaying write data and read data a predetermined number of clock cycles, selectively swapping both most significant write data and read data with least significant write data and read dependent upon memory access control data. The write and read data pass normally for even memory bank accesses and are swapped for odd memory bank accesses. Memory access control data, program counter data and program counter control data are similarly delayed. At least the read data and optionally all the data are held upon a pipeline stall.
摘要翻译：在具有指令流水线的处理器中，跟踪数据通过延迟写入数据并以预定数量的时钟周期读取数据来对准具有指令流水线，有选择地将最重要的写入数据和读取数据与最低有效写入数据进行交换，并依赖于存储器访问控制数据进行读取。写入和读取数据通常用于偶数存储体存取，并被交换用于奇数存储体存取。存储器访问控制数据，程序计数器数据和程序计数器控制数据也被类似地延迟。至少读取的数据和可选地所有的数据被保持在流水线停止。

20. 发明授权

US08401835B2 Trigger ordering for trace streams when multiple triggers accumulate 有权
标题翻译：当多个触发器累积时，触发排序跟踪流
公开(公告)号：US08401835B2
公开(公告)日：2013-03-19
申请号：US10302083
申请日：2002-11-22
申请人： Manisha Agarwala , John M. Johnsen , Lewis Nardini
发明人： Manisha Agarwala , John M. Johnsen , Lewis Nardini
IPC分类号： G06F9/455 , G06F11/00
CPC分类号： G06F11/3636
摘要： In the case of tracing processor activity and generating data streams multiple triggers can be generated at the same time. The issue is further complicated in a protected pipeline where certain locations are considered as in illegal instruction boundary. During those cycles certain information is invalid and cannot be transmitted to the user. Thus a received trace trigger cannot begin. This invention resolves all ambiguities related to multiple triggers so that the user has a known predictable behavior based on the setup of the triggers.
摘要翻译：在跟踪处理器活动和生成数据流的情况下，可以同时生成多个触发器。这个问题在受保护的管道中进一步复杂化，其中某些位置被视为非法指令边界。在这些周期中，某些信息是无效的，不能发送给用户。因此，接收到的跟踪触发器不能开始。本发明解决了与多个触发相关的所有歧义，使得用户基于触发器的设置具有已知的可预测行为。

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