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    • 15. 发明申请
    • HIGH PERFORMANCE 3D FET STRUCTURES, AND METHODS FOR FORMING THE SAME USING PREFERENTIAL CRYSTALLOGRAPHIC ETCHING
    • 高性能3D FET结构及其使用优选结晶蚀刻形成其的方法
    • US20070298552A1
    • 2007-12-27
    • US11851464
    • 2007-09-07
    • Thomas DyerHaining Yang
    • Thomas DyerHaining Yang
    • H01L21/84
    • H01L21/823807H01L21/823821H01L27/0922H01L27/1211H01L29/04H01L29/66795H01L29/7853
    • The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs). Specifically, a 3D semiconductor structure having a bottom surface oriented along one of a first set of equivalent crystal planes and multiple additional surfaces oriented along a second, different set of equivalent crystal planes can be used to form a high performance 3D FET with carrier channels oriented along the second, different set of equivalent crystal planes. More importantly, such a 3D semiconductor structure can be readily formed over the same substrate with an additional 3D semiconductor structure having a bottom surface and multiple additional surfaces all oriented along the first set of equivalent crystal planes. The additional 3D semiconductor structure can be used to form an additional 3D FET, which is complementary to the above-described 3D FET and has carrier channels oriented along the first set of equivalent crystal planes.
    • 本发明涉及高性能三维(3D)场效应晶体管(FET)。 具体而言,可以使用具有沿着第一组等效晶面中的一个取向的底表面和沿着第二不同组的等效晶面取向的多个附加表面的3D半导体结构,以形成具有载体通道定向的高性能3D FET 沿着第二个不同组的等效晶面。 更重要的是,这种3D半导体结构可以容易地在具有底表面和多个附加表面的附加3D半导体结构的同一衬底上形成,所述另外的三维半导体结构全部沿着第一组等效晶面取向。 附加的3D半导体结构可以用于形成附加的3D FET,其与上述3D FET互补,并且具有沿着第一组等效晶面取向的载流子通道。
    • 19. 发明申请
    • ION IMPLANTATION OF NITROGEN INTO SEMICONDUCTOR SUBSTRATE PRIOR TO OXIDATION FOR OFFSET SPACER FORMATION
    • 在离子间隙形成的氧化物之前将氮离子注入半导体衬底
    • US20070114605A1
    • 2007-05-24
    • US11164376
    • 2005-11-21
    • Thomas DyerJinghong LiZhijiong Luo
    • Thomas DyerJinghong LiZhijiong Luo
    • H01L29/78H01L21/336
    • H01L21/26506H01L21/2658H01L21/28247
    • A method of formation of integrated circuit devices includes forming a gate electrode stack over a portion of a semiconductor. The stack includes a gate dielectric layer with a gate electrode thereabove. Implant diatomic nitrogen and/or nitrogen atoms into the substrate aside from the stack at a maximum energy less than or equal to 10 keV for diatomic nitrogen and at a maximum energy less than or equal to 5 keV for atomic nitrogen at a temperature less than or equal to 1000° C. for a time of less than or equal to 30 minutes. Then form silicon oxide offset spacers on sidewalls of the stack. Form source/drain extension regions in the substrate aside from the offset spacers. Form nitride sidewall spacers on outer surfaces of the offset spacers over another portion of the nitrogen implanted layer. Then form source/drain regions in the substrate aside from the sidewall spacers.
    • 形成集成电路器件的方法包括在半导体的一部分上形成栅电极堆叠。 堆叠包括其上方具有栅电极的栅介质层。 将双原子氮和/或氮原子从堆叠中以最低能量小于或等于10keV的双原子氮并且在小于或等于5keV的最大能量下,在低于或等于 等于1000℃,时间小于或等于30分钟。 然后在堆叠的侧壁上形成氧化硅偏移间隔物。 在偏移间隔物之外的衬底中形成源极/漏极延伸区域。 在氮注入层的另一部分上的偏移间隔物的外表面上形成氮化物侧壁间隔物。 然后在侧壁间隔物之外形成衬底中的源极/漏极区域。