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11. 发明授权

US08171259B2 Multi-cluster dynamic reconfigurable circuit for context valid processing of data by clearing received data with added context change indicative signal 有权
标题翻译：多集群动态可重构电路，用于通过用添加的上下文改变指示信号清除接收到的数据来上下文有效地处理数据
公开(公告)号：US08171259B2
公开(公告)日：2012-05-01
申请号：US12394863
申请日：2009-02-27
申请人： Takashi Hanai , Shinichi Sutou
发明人： Takashi Hanai , Shinichi Sutou
IPC分类号： G06F15/16
CPC分类号： G06F9/3885 , G06F9/30072 , G06F9/3879 , G06F9/3891 , G06F9/3897 , G06F15/7867
摘要： A dynamic reconfigurable circuit includes multiple clusters each including a group of reconfigurable processing elements. The dynamic reconfigurable circuit is capable of dynamically changing a configuration of the clusters according to a context including a description of processing of the processing elements and of connection between the processing elements. A first cluster among the clusters includes a signal generating circuit that when an instruction to change the context is received, generates a report signal indicative of the instruction to change the context; a signal adding circuit that adds the report signal generated by the signal generating circuit to output data that is to be transmitted from the first cluster to a second cluster; and a data clearing circuit that, when output data to which a report signal generated by the second cluster is added is received, performs a clearing process of clearing the output data received.
摘要翻译：动态可重构电路包括多个簇，每个簇包括一组可重构处理元件。动态可重构电路能够根据包括处理元件的处理描述和处理元件之间的连接的上下文来动态地改变簇的配置。簇中的第一簇包括信号发生电路，当接收到改变上下文的指令时，产生指示改变上下文的指令的报告信号; 信号添加电路，其将由所述信号发生电路生成的所述报告信号与从所述第一簇发送到第二簇的输出数据相加; 以及数据清除电路，当接收到添加了由第二群集生成的报告信号的输出数据时，执行清除所接收的输出数据的清除处理。

12. 发明授权

US07996661B2 Loop processing counter with automatic start time set or trigger modes in context reconfigurable PE array 有权
标题翻译：循环处理计数器，具有自动启动时间设置或上下文可重构PE阵列中的触发模式
公开(公告)号：US07996661B2
公开(公告)日：2011-08-09
申请号：US12232462
申请日：2008-09-17
申请人： Takashi Hanai , Shinichi Sutou , Masaki Arai , Mitsuharu Wakayoshi
发明人： Takashi Hanai , Shinichi Sutou , Masaki Arai , Mitsuharu Wakayoshi
IPC分类号： G06F9/30
CPC分类号： G06F9/325 , G06F9/3842 , G06F9/3885 , G06F9/3897 , G06F15/7867
摘要： A dynamic reconfigurable circuit that implements optional processing by dynamically switching a processing content of a reconfigurable processing element (PE) and a connection content between the PEs in accordance with a context, includes: a configuration register section for setting a content of loop processing on the basis of the context, the loop processing content including an output source of an output signal from each of a set of the reconfigured PEs, an output destination of the output signal, and a condition for outputting the output signal to the output destination; and at least one counter circuit including a loop control section and an output register section that implement the set loop processing, that count the number of implementations of the loop processing implemented by the loop control section, and that output the output signal to the output destination based on the counted number of implementations and the condition.
摘要翻译：一种动态可重构电路，其通过根据上下文动态切换可重构处理元件（PE）的处理内容和PE之间的连接内容来实现可选处理，包括：配置寄存器部分，用于在上下文的基础，循环处理内容包括来自一组重新配置的PE中的每一个的输出信号的输出源，输出信号的输出目的地以及用于将输出信号输出到输出目的地的条件; 以及至少一个计数器电路，包括循环控制部分和实现设置循环处理的输出寄存器部分，其对由循环控制部分实现的循环处理的执行次数进行计数，并将输出信号输出到输出目的地基于计数的实施数量和条件。

13. 发明授权

US08539415B2 Reconfigurable circuit, its design method, and design apparatus 有权
标题翻译：可重构电路，其设计方法和设计装置
公开(公告)号：US08539415B2
公开(公告)日：2013-09-17
申请号：US12635347
申请日：2009-12-10
申请人： Shinichi Sutou
发明人： Shinichi Sutou
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F15/7867 , G06F17/5045
摘要： A reconfigurable circuit design method includes an input step of inputting design data of a default configuration of a reconfigurable circuit including a plurality of processor elements which perform processing and a first generation step of generating design data obtained by modifying at least one of the processor elements in the reconfigurable circuit with the default configuration.
摘要翻译：可重构电路设计方法包括：输入步骤，输入包括执行处理的多个处理器元件的可重构电路的默认配置的设计数据;以及第一生成步骤，生成通过修改至少一个处理器元件而获得的设计数据可重配置电路具有默认配置。

14. 发明授权

US08291360B2 Data conversion apparatus, method, and computer-readable recording medium storing program for generating circuit configuration information from circuit description 有权
标题翻译：数据转换装置，方法以及用于从电路描述产生电路配置信息的计算机可读记录介质存储程序
公开(公告)号：US08291360B2
公开(公告)日：2012-10-16
申请号：US12503455
申请日：2009-07-15
申请人： Hayato Higuchi , Shinichi Sutou , Tsuguchika Tabaru , Manabu Matsuyama , Ryuichi Ohzeki , Toshihiro Suzuki
发明人： Hayato Higuchi , Shinichi Sutou , Tsuguchika Tabaru , Manabu Matsuyama , Ryuichi Ohzeki , Toshihiro Suzuki
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A data conversion apparatus for converting circuit description related to a dynamically-reconfigurable circuit to circuit configuration information, the data conversion apparatus includes a first generation section that generates a data flow graph from the circuit description; a segment count determining section that determines a number of segments for segmenting the data flow graph generated by the first generation section; a virtual circuit creating section that creates a virtual circuit that has as many resources of the dynamically-reconfigurable circuit as the number of the resources multiplied by the number of segments determined by the segment count determining section; a second generation section that generates, from the circuit description, a data flow graph corresponding to the virtual circuit created by the virtual circuit creating section; and a conversion section that allocates and adjusts the resources of the virtual circuit in accordance with the data flow graph.
摘要翻译：一种用于将与动态可重构电路有关的电路描述转换为电路配置信息的数据转换装置，所述数据转换装置包括从电路描述生成数据流图的第一生成部分; 段计数确定部分，确定用于分割由第一代部分生成的数据流图的段数; 虚拟电路创建部分，其创建虚拟电路，所述虚拟电路具有与所述段计数确定部确定的所述资源的数量相乘的所述动态可重配置电路的资源数量; 第二代部分，从电路描述生成与由虚拟电路创建部分创建的虚拟电路对应的数据流图; 以及根据数据流图分配和调整虚拟电路的资源的转换部分。

15. 发明授权

US5781560A System testing device and method using JTAG circuit for testing high-package density printed circuit boards 失效
标题翻译：使用JTAG电路测试高封装密度印刷电路板的系统测试装置和方法
公开(公告)号：US5781560A
公开(公告)日：1998-07-14
申请号：US902950
申请日：1997-07-30
申请人： Kayoko Kawano , Yasushi Takaki , Shinichi Sutou , Kazuhiro Hara
发明人： Kayoko Kawano , Yasushi Takaki , Shinichi Sutou , Kazuhiro Hara
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/22 , G06F11/273
CPC分类号： G06F11/2736 , G01R31/318536
摘要： A method and system testing device for testing a printed circuit board includes a JTAG circuit provided with a JTAG instruction storage unit for storing a command to control a system logic circuit; and a JTAG data storage unit for storing data used to control the system logic circuit. The system testing device tests the system logic circuit in an LSI by selectively inputting/outputting data to a boundary scan register, a bypass register, the JTAG instruction storage unit, and the JTAG data storage unit.
摘要翻译：一种用于测试印刷电路板的方法和系统测试装置包括一个JTAG电路，该JTAG电路设有用于存储控制系统逻辑电路的命令的JTAG指令存储单元; 以及用于存储用于控制系统逻辑电路的数据的JTAG数据存储单元。系统测试装置通过选择性地向边界扫描寄存器，旁路寄存器，JTAG指令存储单元和JTAG数据存储单元输入/输出数据来测试LSI中的系统逻辑电路。

16. 发明申请

US20120319338A1 COVER MEMBER AND SUSPENSION 有权
标题翻译：盖会员和暂停
公开(公告)号：US20120319338A1
公开(公告)日：2012-12-20
申请号：US13324697
申请日：2011-12-13
申请人： Akira Takada , Shinichi Sutou
发明人： Akira Takada , Shinichi Sutou
IPC分类号： B60G15/06 , F16F13/00 , B32B3/30
CPC分类号： F16F9/38
摘要： A cover member having plural peak portions and plural trough portions, and freely stretched and shrunk in an array direction of the plural peak portions and the plural trough portions or freely bent, the cover member includes: a hollow part formed in each of the plural peak portions, the hollow part being hollowed toward an inner side from a peak of each of the plural peak portions, being formed in a circumferential direction, and having edge parts, a bottom part and side parts located between the edge parts and the bottom part. The edge parts of the hollow part are brought into contact with each other before the side parts of the hollow part are brought into contact with each other, when at least one of the plural peak portions is subjected to force in a direction intersecting with the array direction from an outside.
摘要翻译：一种盖构件，具有多个峰部和多个谷部，并且在所述多个峰部和所述多个谷部的排列方向上自由伸缩并自由弯曲，所述盖构件包括：形成在所述多个峰所述中空部从所述多个峰部中的每一个峰的内侧向内侧中空化，沿圆周方向形成，并且具有边缘部，底部和位于所述边缘部和所述底部之间的侧部。当中空部分的边缘部分彼此接触时，中空部分的边缘部分彼此接触，当多个峰部中的至少一个在与阵列相交的方向上施加力时方向从外面。

17. 发明申请

US20100017761A1 DATA CONVERSION APPARATUS, DATA CONVERSION METHOD, AND COMPUTER-READABLE RECORDING MEDIUM STORING PROGRAM 有权
标题翻译：数据转换装置，数据转换方法和计算机可读记录媒体存储程序
公开(公告)号：US20100017761A1
公开(公告)日：2010-01-21
申请号：US12503455
申请日：2009-07-15
申请人： Hayato HIGUCHI , Shinichi Sutou , Tsuguchika Tabaru , Manabu Matsuyama , Ryuichi Ohzeki , Toshihiro Suzuki
发明人： Hayato HIGUCHI , Shinichi Sutou , Tsuguchika Tabaru , Manabu Matsuyama , Ryuichi Ohzeki , Toshihiro Suzuki
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A data conversion apparatus for converting circuit description related to a dynamically-reconfigurable circuit to circuit configuration information, the data conversion apparatus includes a first generation section that generates a data flow graph from the circuit description; a segment count determining section that determines a number of segments for segmenting the data flow graph generated by the first generation section; a virtual circuit creating section that creates a virtual circuit that has as many resources of the dynamically-reconfigurable circuit as the number of the resources multiplied by the number of segments determined by the segment count determining section; a second generation section that generates, from the circuit description, a data flow graph corresponding to the virtual circuit created by the virtual circuit creating section; and a conversion section that allocates and adjusts the resources of the virtual circuit in accordance with the data flow graph.
摘要翻译：一种用于将与动态可重构电路有关的电路描述转换为电路配置信息的数据转换装置，所述数据转换装置包括从电路描述生成数据流图的第一生成部分; 段计数确定部分，确定用于分割由第一代部分生成的数据流图的段数; 虚拟电路创建部分，其创建虚拟电路，所述虚拟电路具有与所述段计数确定部确定的所述资源的数量相乘的所述动态可重配置电路的资源数量; 第二代部分，从电路描述生成与由虚拟电路创建部分创建的虚拟电路对应的数据流图; 以及根据数据流图分配和调整虚拟电路的资源的转换部分。

18. 发明授权

US08657270B2 Cover member and suspension 有权
标题翻译：封面和悬挂
公开(公告)号：US08657270B2
公开(公告)日：2014-02-25
申请号：US13324697
申请日：2011-12-13
申请人： Akira Takada , Shinichi Sutou
发明人： Akira Takada , Shinichi Sutou
IPC分类号： F16F9/38
CPC分类号： F16F9/38
摘要： A cover member having plural peak portions and plural trough portions, and freely stretched and shrunk in an array direction of the plural peak portions and the plural trough portions or freely bent, the cover member includes: a hollow part formed in each of the plural peak portions, the hollow part being hollowed toward an inner side from a peak of each of the plural peak portions, being formed in a circumferential direction, and having edge parts, a bottom part and side parts located between the edge parts and the bottom part. The edge parts of the hollow part are brought into contact with each other before the side parts of the hollow part are brought into contact with each other, when at least one of the plural peak portions is subjected to force in a direction intersecting with the array direction from an outside.
摘要翻译：一种盖构件，具有多个峰部和多个谷部，并且在所述多个峰部和所述多个谷部的排列方向上自由伸缩并自由弯曲，所述盖构件包括：形成在所述多个峰所述中空部从所述多个峰部中的每一个峰的内侧向内侧中空化，沿圆周方向形成，并且具有边缘部，底部和位于所述边缘部和所述底部之间的侧部。当中空部分的边缘部分彼此接触时，中空部分的边缘部分彼此接触，当多个峰部中的至少一个在与阵列相交的方向上施加力时方向从外面。

19. 发明授权

US08359419B2 System LSI having plural buses 有权
标题翻译：具有多个总线的系统LSI
公开(公告)号：US08359419B2
公开(公告)日：2013-01-22
申请号：US12617291
申请日：2009-11-12
申请人： Shinichi Sutou , Kiyomitsu Katou
发明人： Shinichi Sutou , Kiyomitsu Katou
IPC分类号： G06F13/14
CPC分类号： G06F13/28
摘要： A system LSI includes first and second memories, first and second buses, a bus bridge that performs signal transfer between the first and second buses, a first bus system connecting to the first bus and accessing the first or second memory, a second bus system connecting to the second bus and accessing the first or second memory, a memory access circuit having first and second bus-side input/output terminals that perform signal transfer to/from the first and second buses and first and second memory-side input/output terminals that perform signal transfer to/from the first and second memories.
摘要翻译：系统LSI包括第一和第二存储器，第一和第二总线，执行第一和第二总线之间的信号传送的总线桥，连接到第一总线并访问第一或第二存储器的第一总线系统，连接到第二总线并访问第一或第二存储器，存储器访问电路具有第一和第二总线侧输入/输出端子，其执行到/来自第一和第二总线的信号传送以及第一和第二存储器侧输入/输出端子其执行到/从第一和第二存储器的信号传送。

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