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11. 发明申请

US20110078646A1 SUPPORT APPARATUS AND DESIGN SUPPORT METHOD 有权
标题翻译：支持设备和设计支持方法
公开(公告)号：US20110078646A1
公开(公告)日：2011-03-31
申请号：US12892481
申请日：2010-09-28
申请人： Kenichi Ushiyama , Shigenori Ichinose , Kenji Suzuki , Kenji Kumagai , Takafumi Miyahara , Shuji Tanahashi , Hideto Fukuda
发明人： Kenichi Ushiyama , Shigenori Ichinose , Kenji Suzuki , Kenji Kumagai , Takafumi Miyahara , Shuji Tanahashi , Hideto Fukuda
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A design support method executed by a computer includes: detecting a layout position of a first terminal in a cell as a first layout position from layout data including a cell of a macro which is arranged at a plurality of orientations, the first terminal being arranged at a first orientation; calculating a second layout position of a first terminal which is arranged at a second orientation which is different from the first orientation based on a variation from the first orientation to the second orientation and the first layout position; associating the second layout position with the first layout position and the layout data; and outputting an association result.
摘要翻译：由计算机执行的设计支持方法包括：从包括布置在多个方向上的宏单元的布局数据中检测单元中的第一终端的布局位置作为第一布局位置，所述第一终端布置在第一个方向; 基于从所述第一取向到所述第二取向和所述第一布局位置的变化，计算布置在与所述第一取向不同的第二取向的第一端子的第二布局位置; 将第二布局位置与第一布局位置和布局数据相关联; 并输出关联结果。

12. 发明授权

US07339250B2 Semiconductor integrated circuit having reduced cross-talk noise 有权
标题翻译：半导体集成电路具有降低的串扰噪声
公开(公告)号：US07339250B2
公开(公告)日：2008-03-04
申请号：US10914163
申请日：2004-08-10
申请人： Kenichi Ushiyama , Shigenori Ichinose
发明人： Kenichi Ushiyama , Shigenori Ichinose
IPC分类号： H01L29/00 , H01L23/552
CPC分类号： H01L23/5225 , G06F17/5077 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit includes a shielded wire line and a shielding wire line provided for the shielded wire line and divided into a plurality of segments in a longitudinal direction of the shielded wire line.
摘要翻译：半导体集成电路包括屏蔽线和屏蔽线线设置的屏蔽线，并且在屏蔽线的纵向上分为多个段。

13. 发明授权

US07219320B2 Semiconductor integrated circuit timing analysis apparatus timing analysis method and timing analysis program 失效
标题翻译：半导体集成电路定时分析装置定时分析方法和时序分析程序
公开(公告)号：US07219320B2
公开(公告)日：2007-05-15
申请号：US10807286
申请日：2004-03-24
申请人： Tetsuo Kawano , Satoru Yoshikawa , Toshikatsu Hosono , Shigenori Ichinose , Takashi Yoneda
发明人： Tetsuo Kawano , Satoru Yoshikawa , Toshikatsu Hosono , Shigenori Ichinose , Takashi Yoneda
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： OCV coefficients in a path being an analysis target according to the number of gate stages are calculated in a coefficient arithmetically operating unit by canceling off a variation in delay in each gate in accordance with the number of gate stages in the target path, and timing analysis of the target path is performed in a timing analysis unit by using the OCV coefficient with the number of gate stages being considered, whereby a variation degree in the entire path is reduced in accordance with the number of gate stages in the target path, thus making it possible to carry out accurate timing analysis in consideration of the variation in a chip of a semiconductor integrated circuit.
摘要翻译：根据栅极级的数量，在系数运算单元中计算作为分析对象的路径中的OCV系数，通过根据目标路径中的门级的数量消除每个门的延迟的变化，以及定时分析通过使用考虑了门级数的OCV系数在定时分析单元中执行目标路径的变化，从而根据目标路径中的门级数减少整个路径的变化程度，从而使考虑到半导体集成电路的芯片的变化，可以进行准确的时序分析。

14. 发明授权

US06467070B2 Design support apparatus for semiconductor devices 失效
标题翻译：半导体器件设计支持设备
公开(公告)号：US06467070B2
公开(公告)日：2002-10-15
申请号：US09808344
申请日：2001-03-15
申请人： Sachi Kuroda , Toshiaki Sugioka , Toru Osajima , Shigenori Ichinose
发明人： Sachi Kuroda , Toshiaki Sugioka , Toru Osajima , Shigenori Ichinose
IPC分类号： G06F1750
CPC分类号： G06F17/5068
摘要： A design support apparatus for semiconductor devices that is used to quickly arrange a non-logic cell for reducing electromagnetic radiation from a semiconductor device at the time of designing it. In this design support apparatus for semiconductor devices, a layout section does a layout for logic cells and wiring patterns to connect the logic cells. An arranged site detecting section detects an arranged site, being a site which contains neither the logic cells nor a prohibited area, after a layout is done by the layout section. A non-logic cell pattern store section stores non-logic cell patterns. A prohibited area containing site detecting section detects a prohibited area containing site, being a site which only contains a prohibited area. A non-logic cell arranging section arranges non-logic cells on the arranged site. Furthermore, the non-logic cell arranging section compares the arrangement of the prohibited area on the prohibited area containing site with a non-logic cell pattern and arranges non-logic cells only on a site where these do not conflict with each other.
摘要翻译：一种用于半导体器件的设计支持装置，其用于在设计时快速地布置用于减少来自半导体器件的电磁辐射的非逻辑单元。在这种用于半导体器件的设计支持装置中，布局部分对逻辑单元和布线图案进行布局以连接逻辑单元。在布局部分进行布局之后，排列位置检测部分检测作为不包含逻辑单元或禁止区域的位置的排列位置。非逻辑单元图形存储部分存储非逻辑单元图案。含有现场检测部分的禁止区域检测禁止区域的包含场地，作为仅包含禁止区域的场所。非逻辑单元布置部分在布置的位置上布置非逻辑单元。此外，非逻辑单元布置部分将禁止区域的禁止区域的布置与非逻辑单元图案进行比较，并且将非逻辑单元仅在彼此不冲突的位置排列。

15. 发明申请

US20080301610A1 Semiconductor integrated circuit having reduced cross-talk noise 有权
公开(公告)号：US20080301610A1
公开(公告)日：2008-12-04
申请号：US12071845
申请日：2008-02-27
申请人： Kenichi Ushiyama , Shigenori Ichinose
发明人： Kenichi Ushiyama , Shigenori Ichinose
IPC分类号： G06F17/50
CPC分类号： H01L23/5225 , G06F17/5077 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit includes a shielded wire line and a shielding wire line provided for the shielded wire line and divided into a plurality of segments in a longitudinal direction of the shielded wire line.

16. 发明授权

US06972493B2 Semiconductor integrated circuit having reduced cross-talk noise 有权
公开(公告)号：US06972493B2
公开(公告)日：2005-12-06
申请号：US10694997
申请日：2003-10-29
申请人： Kenichi Ushiyama , Shigenori Ichinose
发明人： Kenichi Ushiyama , Shigenori Ichinose
IPC分类号： G06F17/50 , H01L21/82 , H01L21/822 , H01L23/522 , H01L27/04 , H01L29/40
CPC分类号： H01L23/5225 , G06F17/5077 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit includes a shielded wire line and a shielding wire line provided for the shielded wire line and divided into a plurality of segments in a longitudinal direction of the shielded wire line.

17. 发明申请

US20050081171A1 Timing analysis apparatus, timing analysis method and program product 失效
标题翻译：定时分析仪器，时序分析方法和程序产品
公开(公告)号：US20050081171A1
公开(公告)日：2005-04-14
申请号：US10807286
申请日：2004-03-24
申请人： Tetsuo Kawano , Satoru Yoshikawa , Toshikatsu Hosono , Shigenori Ichinose , Takashi Yoneda
发明人： Tetsuo Kawano , Satoru Yoshikawa , Toshikatsu Hosono , Shigenori Ichinose , Takashi Yoneda
IPC分类号： G06F17/50 , G06F9/45 , H01L21/82
CPC分类号： G06F17/5031
摘要： OCV coefficients in a path being an analysis target according to the number of gate stages are calculated in a coefficient arithmetically operating unit by canceling off a variation in delay in each gate in accordance with the number of gate stages in the target path, and timing analysis of the target path is performed in a timing analysis unit by using the OCV coefficient with the number of gate stages being considered, whereby a variation degree in the entire path is reduced in accordance with the number of gate stages in the target path, thus making it possible to carry out accurate timing analysis in consideration of the variation in a chip of a semiconductor integrated circuit.
摘要翻译：根据栅极级的数量，在系数运算单元中计算作为分析对象的路径中的OCV系数，通过根据目标路径中的门级的数量消除每个门的延迟的变化，以及定时分析通过使用考虑了门级数的OCV系数在定时分析单元中执行目标路径的变化，从而根据目标路径中的门级数减少整个路径的变化程度，从而使考虑到半导体集成电路的芯片的变化，可以进行准确的时序分析。

18. 发明授权

US06664638B2 Semiconductor integrated circuit having reduced cross-talk noise 有权
公开(公告)号：US06664638B2
公开(公告)日：2003-12-16
申请号：US09963469
申请日：2001-09-27
申请人： Kenichi Ushiyama , Shigenori Ichinose
发明人： Kenichi Ushiyama , Shigenori Ichinose
IPC分类号： H01L2348
CPC分类号： H01L23/5225 , G06F17/5077 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit includes a shielded wire line and a shielding wire line provided for the shielded wire line and divided into a plurality of segments in a longitudinal direction of the shielded wire line.

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