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11. 发明授权

US10103757B2 Method and apparatus to detect LO leakage and image rejection using a single transistor 有权
公开(公告)号：US10103757B2
公开(公告)日：2018-10-16
申请号：US15505444
申请日：2015-08-25
申请人： Tensorcom, Inc.
发明人： KhongMeng Tham , Huainan Ma , Zaw Soe , Ricky Lap Kei Cheung
IPC分类号： H04B1/04 , H03D7/12
摘要： Local oscillator (LO) leakage and Image are common and undesirable effects in typical transmitters. Typically, fairly complex hardware and algorithms are used to calibrate and reduce these impairments. A single transistor that draws essentially no dc current and occupies a very small area detects the LO leakage and Image signals. The single transistor operating as a square-law device is used to mix the signals at the input and output ports of a power amplifier. The mixed signal generated by the single transistor enables the simultaneous calibration of the LO leakage and Image Rejection.

12. 发明申请

US20170272109A1 Method and Apparatus to Detect LO Leakage and Image Rejection using a Single Transistor 审中-公开
公开(公告)号：US20170272109A1
公开(公告)日：2017-09-21
申请号：US15505444
申请日：2015-08-25
申请人： Tensorcom, Inc.
发明人： KhongMeng Tham , Huainan Ma , Zaw Soe , Ricky Lap Kei Cheung
IPC分类号： H04B1/04 , H03D7/12
CPC分类号： H04B1/0475 , H03C2200/0058 , H03D3/008 , H03D3/009 , H03D7/125 , H03D7/165 , H04B1/04 , H04B1/0458 , H04B2001/0408
摘要： Local oscillator (LO) leakage and Image are common and undesirable effects in typical transmitters. Typically, fairly complex hardware and algorithms are used to calibrate and reduce these impairments. A single transistor that draws essentially no dc current and occupies a very small area detects the LO leakage and Image signals. The single transistor operating as a square-law device is used to mix the signals at the input and output ports of a power amplifier. The mixed signal generated by the single transistor enables the simultaneous calibration of the LO leakage and Image Rejection.

13. 发明授权

US09276610B2 Method and apparatus of a fully-pipelined layered LDPC decoder 有权
标题翻译：全流水线分层LDPC解码器的方法和装置
公开(公告)号：US09276610B2
公开(公告)日：2016-03-01
申请号：US14165505
申请日：2014-01-27
申请人： Tensorcom, Inc.
发明人： Bo Xia , Ricky Lap Kei Cheung , Bo Lu
IPC分类号： H03M13/11
CPC分类号： H03M13/1145 , H03M13/1122 , H03M13/114 , H03M13/1148 , H03M13/116
摘要： The architecture is able to switch to Non-blocking check-node-update (CNU) scheduling architecture which has better performance than blocking CNU scheduling architecture. The architecture uses an Offset Min-Sum with Beta=1 with a clock domain operating at 440 MHz. The constraint macro-matrix is a spare matrix where each “1’ corresponds to a sub-array of a cyclically shifted identity matrix which is a shifted version of an identity matrix. Four core processors are used in the layered architecture where the constraint matrix uses a sub-array of 42 (check nodes)×42 (variable nodes) in the macro-array of 168×672 bits. Pipeline processing is used where the delay for each layer only requires 4 clock cycles.
摘要翻译：该架构能够切换到具有比阻塞CNU调度架构更好的性能的非阻塞校验节点更新（CNU）调度体系结构。该架构使用Beta = 1的偏移最小和，时钟域工作在440 MHz。约束宏矩阵是备用矩阵，其中每个“1”对应于作为单位矩阵的移位版本的循环移位单位矩阵的子阵列。在分层架构中使用四个核心处理器，约束矩阵在168×672位的宏阵列中使用42（校验节点）×42（变量节点）的子阵列。使用管道处理，其中每层的延迟只需要4个时钟周期。

14. 发明申请

US20150214980A1 Method and Apparatus of a Fully-Pipelined Layered LDPC Decoder 有权
标题翻译：全流水线分层LDPC解码器的方法和装置
公开(公告)号：US20150214980A1
公开(公告)日：2015-07-30
申请号：US14165505
申请日：2014-01-27
申请人： Tensorcom, Inc.
发明人： Bo Xia , Ricky Lap Kei Cheung , Bo Lu
IPC分类号： H03M13/11
CPC分类号： H03M13/1145 , H03M13/1122 , H03M13/114 , H03M13/1148 , H03M13/116
摘要： The architecture is able to switch to Non-blocking check-node-update (CNU) scheduling architecture which has better performance than blocking CNU scheduling architecture. The architecture uses an Offset Min-Sum with Beta=1 with a clock domain operating at 440 MHz. The constraint macro-matrix is a spare matrix where each “1’ corresponds to a sub-array of a cyclically shifted identity matrix which is a shifted version of an identity matrix. Four core processors are used in the layered architecture where the constraint matrix uses a sub-array of 42 (check nodes)×42 (variable nodes) in the macro-array of 168×672 bits. Pipeline processing is used where the delay for each layer only requires 4 clock cycles.
摘要翻译：该架构能够切换到具有比阻塞CNU调度架构更好的性能的非阻塞校验节点更新（CNU）调度体系结构。该架构使用Beta = 1的偏移最小和，时钟域工作在440 MHz。约束宏矩阵是备用矩阵，其中每个“1”对应于作为单位矩阵的移位版本的循环移位单位矩阵的子阵列。在分层架构中使用四个核心处理器，约束矩阵在168×672位的宏阵列中使用42（校验节点）×42（变量节点）的子阵列。使用管道处理，其中每层的延迟只需要4个时钟周期。

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