专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US07893501B2 Semiconductor device including MISFET having internal stress film 有权
标题翻译：包括具有内部应力膜的MISFET的半导体器件
公开(公告)号：US07893501B2
公开(公告)日：2011-02-22
申请号：US12170191
申请日：2008-07-09
申请人： Masafumi Tsutsui , Hiroyuki Umimoto , Kaori Akamatsu
发明人： Masafumi Tsutsui , Hiroyuki Umimoto , Kaori Akamatsu
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L27/092
摘要： A semiconductor device includes a first-type internal stress film formed of a silicon oxide film over source/drain regions of an nMISFET and a second-type internal stress film formed of a TEOS film over source/drain regions of a pMISFET. In a channel region of the nMISFET, a tensile stress is generated in the direction of movement of electrons due to the first-type internal stress film, so that the mobility of electrons is increased. In a channel region of the pMISFET, a compressive stress is generated in the direction of movement of holes due to the second-type internal stress film, so that the mobility of holes is increased.
摘要翻译：半导体器件包括由nMISFET的源极/漏极区域上的氧化硅膜形成的第一型内部应力膜和在pMISFET的源极/漏极区域上由TEOS膜形成的第二类型内部应力膜。在nMISFET的沟道区域中，由于第一型内应力膜，电子的移动方向产生拉伸应力，使得电子的迁移率增加。在pMISFET的沟道区域中，由于第二类型的内部应力膜，在孔的移动方向上产生压缩应力，使得孔的迁移率增加。

12. 发明授权

US07417289B2 Semiconductor device having internal stress film 有权
标题翻译：具有内部应力膜的半导体器件
公开(公告)号：US07417289B2
公开(公告)日：2008-08-26
申请号：US11730988
申请日：2007-04-05
申请人： Masafumi Tsutsui , Hiroyuki Umimoto , Kaori Akamatsu
发明人： Masafumi Tsutsui , Hiroyuki Umimoto , Kaori Akamatsu
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L27/092
摘要： A semiconductor device includes a first-type internal stress film formed of a silicon oxide film over source/drain regions of an nMISFET and a second-type internal stress film formed of a TEOS film over source/drain regions of a pMISFET. In a channel region of the nMISFET, a tensile stress is generated in the direction of movement of electrons due to the first-type internal stress film, so that the mobility of electrons is increased. In a channel region of the pMISFET, a compressive stress is generated in the direction of movement of holes due to the second-type internal stress film, so that the mobility of holes is increased.
摘要翻译：半导体器件包括由nMISFET的源极/漏极区域上的氧化硅膜形成的第一型内部应力膜和在pMISFET的源极/漏极区域上由TEOS膜形成的第二类型内部应力膜。在nMISFET的沟道区域中，由于第一型内应力膜，电子的移动方向产生拉伸应力，使得电子的迁移率增加。在pMISFET的沟道区域中，由于第二类型的内部应力膜，在孔的移动方向上产生压缩应力，使得孔的迁移率增加。

13. 发明授权

US07067382B2 Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07067382B2
公开(公告)日：2006-06-27
申请号：US10853128
申请日：2004-05-26
申请人： Hiroaki Nakaoka , Kentaro Nakanishi , Hiroyuki Umimoto , Atsuhiro Kajiya
发明人： Hiroaki Nakaoka , Kentaro Nakanishi , Hiroyuki Umimoto , Atsuhiro Kajiya
IPC分类号： H01L21/336
CPC分类号： H01L21/823842
摘要： As first thermal treatment for activating an impurity injected into a gate electrode, thermal treatment at a low temperature for a long time in which boron diffusion into each crystal grain in polysilicon hardly occurs and boron diffusion in each crystal boundary occurs is performed. Next, as second thermal treatment, thermal treatment at a high temperature for a short time, such as spike annealing and flash annealing, in which impurity diffusion into each crystal grain in a polysilicon layer occurs is performed.
摘要翻译：作为用于激活注入到栅电极中的杂质的第一热处理，进行长时间的低温热处理，其中几乎不会发生多晶硅中每个晶粒中的硼扩散，并且发生每个晶体边界中的硼扩散。接下来，作为第二热处理，进行其中发生在多晶硅层中的每个晶粒中的杂质扩散的短时间的高温处理，例如尖峰退火和闪光退火。

14. 发明申请

US20050087818A1 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050087818A1
公开(公告)日：2005-04-28
申请号：US10601557
申请日：2003-06-24
申请人： Masahiro Imade , Tadashi Kadowaki , Hiroyuki Umimoto
发明人： Masahiro Imade , Tadashi Kadowaki , Hiroyuki Umimoto
IPC分类号： H01L29/786 , H01L21/28 , H01L21/336 , H01L29/423 , H01L29/76 , H01L29/78
CPC分类号： H01L29/6653 , H01L29/4232 , H01L29/6659 , H01L29/7833 , Y10S257/90
摘要： A substrate 11 consists of a semiconductor layer 12 as an element formation region and an STI 13 as an isolation region. A gate dielectric 15 is provided on the semiconductor layer 12, and a gate electrode 14 is provided to extend from the top of the gate dielectric 15 to the top of the STI 13. A sidewall 30 for covering the sides of the gate electrode 14 is provided to extend across the top of the semiconductor layer 12 to the tops of regions of the STI 13 adjacent to the outer edges of the semiconductor layer 12. The sidewall 30 is employed as an ion implantation mask for forming high-concentration impurity diffusion layers 16 each serving as a source/drain region.
摘要翻译：衬底11由作为元件形成区域的半导体层12和作为隔离区域的STI 13组成。栅极电介质15设置在半导体层12上，并且栅电极14设置为从栅极电介质15的顶部延伸到STI 13的顶部。用于覆盖栅电极14的侧面的侧壁30是被提供以跨越半导体层12的顶部延伸到与半导体层12的外边缘相邻的STI 13的区域的顶部。侧壁30用作用于形成高浓度杂质扩散层16的离子注入掩模每个都用作源/漏区。

15. 发明授权

US06764921B2 Semiconductor device and method for fabricating the same 有权
公开(公告)号：US06764921B2
公开(公告)日：2004-07-20
申请号：US10630800
申请日：2003-07-31
申请人： Masahiro Imade , Hiroyuki Umimoto
发明人： Masahiro Imade , Hiroyuki Umimoto
IPC分类号： H01L2176
CPC分类号： H01L21/76224 , H01L21/823481 , H01L29/78
摘要： A semiconductor device of the present invention includes a MISFET provided in an element formation region Re of a semiconductor substrate 11 and a trench isolation 13 surrounding the sides of the element formation region Re. An oxygen-passage-suppression film 23 is provided from the top of the trench isolation 13 to the top of a portion of the element formation region Re adjacent to the trench isolation 13. The oxygen-passage-suppression film 23 is made of a silicon nitride film or the like through which oxygen is less likely to permeate. Therefore, since it becomes hard that the upper edge of the element formation region Re of the semiconductor substrate 11 is oxidized, an expansion of the volume of the upper edge is suppressed, thereby reducing a stress.

16. 发明授权

US5455205A Method of producing semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US5455205A
公开(公告)日：1995-10-03
申请号：US34763
申请日：1993-03-19
申请人： Hiroyuki Umimoto , Shin Hashimoto , Shinji Odanaka
发明人： Hiroyuki Umimoto , Shin Hashimoto , Shinji Odanaka
IPC分类号： H01L21/3105 , H01L21/8242 , H01L27/105 , H01L27/108 , H01L21/02
CPC分类号： H01L27/10852 , H01L21/3105 , H01L27/108 , H01L27/105 , Y10S148/133 , Y10S438/978
摘要： There is disclosed a method of producing a semiconductor memory device. An interlayer insulation film is formed on a semiconductor substrate including a switching transistor. Then, a memory node pattern reaching an active region of the switching transistor is formed. A cell plate electrode pattern is formed through an insulation film formed on the memory node in such a manner that a value obtained by subtracting a thickness of a polycrystalline silicon film for a cell plate electrode from an overlapping dimension of a memory node pattern and the cell plate electrode pattern is not less than two times larger and not more than ten times larger than a thickness of deposition of a BPSG film. Then, the BPSG film is deposited on an entire surface, and then is caused to viscously flow by a heat treatment. Then, an aluminum wiring is formed on the BPSG film. With this construction, a step of the aluminum wiring in a boundary region between a memory cell array portion and a peripheral circuit portion, or in a word line-backing contact forming region, is decreased, thereby preventing the lowering of the yield of the aluminum wiring which is caused by the cutting of the aluminum wiring and the remaining of a residue of etching for a contact-forming electrode (for example, tungsten).
摘要翻译：公开了一种制造半导体存储器件的方法。在包括开关晶体管的半导体衬底上形成层间绝缘膜。然后，形成到达开关晶体管的有源区的存储器节点图形。通过形成在存储节点上的绝缘膜形成单元板电极图案，使得通过从存储器节点图案和单元的重叠尺寸减去用于单元板电极的多晶硅膜的厚度而获得的值平板电极图案不小于BPSG膜的沉积厚度的两倍以上且不大于十倍。然后，将BPSG膜沉积在整个表面上，然后通过热处理使其粘稠流动。然后，在BPSG膜上形成铝布线。利用这种结构，在存储单元阵列部分和外围电路部分之间或字线 - 背衬接触形成区域中的边界区域中的铝布线的步骤减小，从而防止铝的收率降低通过切割铝布线引起的布线和剩余的用于接触形成电极（例如钨）的蚀刻残留物。

17. 发明授权

US07205615B2 Semiconductor device having internal stress film 有权
标题翻译：具有内部应力膜的半导体器件
公开(公告)号：US07205615B2
公开(公告)日：2007-04-17
申请号：US10859219
申请日：2004-06-03
申请人： Masafumi Tsutsui , Hiroyuki Umimoto , Kaori Akamatsu
发明人： Masafumi Tsutsui , Hiroyuki Umimoto , Kaori Akamatsu
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L27/092
摘要： A semiconductor device includes a first-type internal stress film formed of a silicon oxide film over source/drain regions of an nMISFET and a second-type internal stress film formed of a TEOS film over source/drain regions of a pMISFET. In a channel region of the nMISFET, a tensile stress is generated in the direction of movement of electrons due to the first-type internal stress film, so that the mobility of electrons is increased. In a channel region of the pMISFET, a compressive stress is generated in the direction of movement of holes due to the second-type internal stress film, so that the mobility of holes is increased.
摘要翻译：半导体器件包括由nMISFET的源极/漏极区域上的氧化硅膜形成的第一型内部应力膜和在pMISFET的源极/漏极区域上由TEOS膜形成的第二类型内部应力膜。在nMISFET的沟道区域中，由于第一型内应力膜，电子的移动方向产生拉伸应力，使得电子的迁移率增加。在pMISFET的沟道区域中，由于第二类型的内部应力膜，在孔的移动方向上产生压缩应力，使得孔的迁移率增加。

18. 发明授权

US06921933B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06921933B2
公开(公告)日：2005-07-26
申请号：US10713221
申请日：2003-11-17
申请人： Hiroyuki Umimoto , Shinji Odanaka
发明人： Hiroyuki Umimoto , Shinji Odanaka
IPC分类号： H01L21/265 , H01L21/336 , H01L29/10 , H01L29/76
CPC分类号： H01L29/6659 , H01L21/26513 , H01L29/1083 , H01L29/66492
摘要： A gate electrode is formed on a semiconductor substrate with agate insulating film interposed therebetween. A channel region composed of a first-conductivity-type semiconductor layer is formed in a region of a surface portion of the semiconductor substrate located below the gate electrode. Source/drain regions each composed of a second-conductivity-type impurity layer are formed in regions of the surface portion of the semiconductor substrate located on both sides of the gate electrode. Second-conductivity-type extension regions are formed between the channel region and respective upper portion of the source/drain regions in contact relation with the source/drain regions. First-conductivity-type pocket regions are formed between the channel region and respective lower portion of the source/drain regions in contact relation with the source/drain regions and in spaced relation to the gate insulating film.
摘要翻译：在半导体衬底上形成有栅电极，其间插有玛瑙绝缘膜。在位于栅电极下方的半导体衬底的表面部分的区域中形成由第一导电型半导体层构成的沟道区。在位于栅电极两侧的半导体衬底的表面部分的区域中形成各自由第二导电型杂质层构成的源/漏区。第二导电型延伸区域形成在与源极/漏极区域接触的沟道区域和源极/漏极区域的相应上部之间。第一导电型袋区域形成在沟道区域和与源极/漏极区域接触的源极/漏极区域的相应下部，并且与栅极绝缘膜间隔开。

19. 发明授权

US06768201B1 Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06768201B1
公开(公告)日：2004-07-27
申请号：US10618730
申请日：2003-07-15
申请人： Masahiro Imade , Hiroyuki Umimoto , Satoe Miyata
发明人： Masahiro Imade , Hiroyuki Umimoto , Satoe Miyata
IPC分类号： H01L2348
CPC分类号： H01L23/62 , H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor device according to the present invention, an n-type MISFET 12 including a semiconductor substrate 11, a source region 16, a drain region 17 and a gate electrode 19 is provided. On the semiconductor substrate 11, a first interlevel insulating film 13 covering the MISFET 12, a second interlevel insulating film 14 and third interlevel insulating film 15 are provided. On the first interlevel insulating film 13, a first gate interconnect 25 for electrically connecting a gate electrode 19 and the outside, a first drain interconnect for electrically connecting the drain region and the outside are provided so as to face each other with part of a second interlevel insulating film 14 interposed therebetween.
摘要翻译：在根据本发明的半导体器件中，提供了包括半导体衬底11，源极区16，漏极区17和栅极电极19的n型MISFET 12。在半导体基板11上设置覆盖MISFET12的第一层间绝缘膜13，第二层间绝缘膜14和第三层间绝缘膜15。在第一层间绝缘膜13上，设置用于电连接栅极电极19和外部的第一栅极互连25，用于电连接漏极区域和外部的第一漏极互连件，插入其间的层间绝缘膜14。

20. 发明授权

US06660601B2 Semiconductor device and method for fabricating the same 失效
公开(公告)号：US06660601B2
公开(公告)日：2003-12-09
申请号：US09938527
申请日：2001-08-27
申请人： Satoe Miyata , Hiroyuki Umimoto , Michikazu Matsumoto , Susumu Akamatsu
发明人： Satoe Miyata , Hiroyuki Umimoto , Michikazu Matsumoto , Susumu Akamatsu
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/324 , H01L29/6656 , H01L29/7833
摘要： Ions of boron as a dopant are implanted using a gate electrode and an isolation film as a mask, thereby forming an ion-implanted layer as a prototype for an extended heavily doped layer. In this process step, a peak concentration of the dopant existing in the ion-implanted layer is set close to, and equal to or less than, a solid solubility at a process temperature for a first annealing process. Then, almost all of the dopant existing in the extended heavily doped layer is activated by performing the first annealing process. Thereafter, a sidewall and an ion-implanted layer as a prototype for a heavily doped source/drain layer are formed, and then the heavily doped source/drain layer is defined by performing a second RTA process.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式