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11. 发明申请

US20080171415A1 Methods of Forming NAND Memory with Virtual Channel 有权
标题翻译：用虚拟通道形成NAND存储器的方法
公开(公告)号：US20080171415A1
公开(公告)日：2008-07-17
申请号：US11626784
申请日：2007-01-24
申请人： Henry Chien , George Matamis , Takashi Orimoto , James Kai
发明人： Henry Chien , George Matamis , Takashi Orimoto , James Kai
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A string of nonvolatile memory cells are connected together by source/drain regions that include an inversion layer created by fixed charge in an overlying layer. Control gates extend between floating gates so that two control gates couple to a floating gate. A fixed charge layer may be formed by plasma nitridation.
摘要翻译：一系列非易失性存储单元通过源/漏区连接在一起，其包括在上层中由固定电荷产生的反型层。控制栅极在浮动栅极之间延伸，使得两个控制栅极耦合到浮动栅极。可以通过等离子体氮化形成固定电荷层。

12. 发明授权

US07795080B2 Methods of forming integrated circuit devices using composite spacer structures 有权
标题翻译：使用复合间隔结构形成集成电路器件的方法
公开(公告)号：US07795080B2
公开(公告)日：2010-09-14
申请号：US12014689
申请日：2008-01-15
申请人： Takashi Orimoto , George Matamis , James Kai , Tuan Pham , Masaaki Higashitani , Henry Chien
发明人： Takashi Orimoto , George Matamis , James Kai , Tuan Pham , Masaaki Higashitani , Henry Chien
IPC分类号： H01L21/82
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11521
摘要： Methods of fabricating integrated circuit devices are provided using composite spacer formation processes. A composite spacer structure is used to pattern and etch the layer stack when forming select features of the devices. A composite storage structure includes a first spacer formed from a first layer of spacer material and second and third spacers formed from a second layer of spacer material. The process is suitable for making devices with line and space sizes at less then the minimum resolvable feature size of the photolithographic processes being used. Moreover, equal line and space sizes at less than the minimum feature size are possible. In one embodiment, an array of dual control gate non-volatile flash memory storage elements is formed using composite spacer structures. When forming the active areas of the substrate, with overlying strips of a layer stack and isolation regions therebetween, a composite spacer structure facilitates equal lengths of the strips and isolation regions therebetween.
摘要翻译：使用复合间隔物形成工艺提供制造集成电路器件的方法。当形成设备的选择特征时，使用复合间隔物结构来图案化和蚀刻层堆叠。复合存储结构包括由第一隔离物材料层形成的第一间隔物和由第二隔离物材料层形成的第二和第三间隔物。该方法适用于制造具有小于所使用的光刻工艺的最小可分辨特征尺寸的线和空间尺寸的装置。此外，等于线和空间尺寸小于最小特征尺寸是可能的。在一个实施例中，使用复合间隔结构形成双控制非易失性闪存存储元件阵列。当形成衬底的活性区域时，具有叠层的叠层和隔离区之间的复合间隔结构有利于条之间的等长长度和隔离区。

13. 发明授权

US07495282B2 NAND memory with virtual channel 有权
标题翻译：具有虚拟通道的NAND内存
公开(公告)号：US07495282B2
公开(公告)日：2009-02-24
申请号：US11626778
申请日：2007-01-24
申请人： Takashi Orimoto , James Kai , Henry Chien , George Matamis
发明人： Takashi Orimoto , James Kai , Henry Chien , George Matamis
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A string of nonvolatile memory cells are connected together by source/drain regions that include an inversion layer created by fixed charge in an overlying layer. Control gates extend between floating gates so that two control gates couple to a floating gate. A fixed charge layer may be formed by plasma nitridation.
摘要翻译：一系列非易失性存储单元通过源/漏区连接在一起，其包括在上层中由固定电荷产生的反型层。控制栅极在浮动栅极之间延伸，使得两个控制栅极耦合到浮动栅极。可以通过等离子体氮化形成固定电荷层。

14. 发明申请

US20080170438A1 NAND Memory with Virtual Channel 有权
标题翻译： NAND存储器与虚拟通道
公开(公告)号：US20080170438A1
公开(公告)日：2008-07-17
申请号：US11626778
申请日：2007-01-24
申请人： Takashi Orimoto , James Kai , Henry Chien , George Matamis
发明人： Takashi Orimoto , James Kai , Henry Chien , George Matamis
IPC分类号： G11C11/34
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A string of nonvolatile memory cells are connected together by source/drain regions that include an inversion layer created by fixed charge in an overlying layer. Control gates extend between floating gates so that two control gates couple to a floating gate. A fixed charge layer may be formed by plasma nitridation.
摘要翻译：一系列非易失性存储单元通过源/漏区连接在一起，其包括在上层中由固定电荷产生的反型层。控制栅极在浮动栅极之间延伸，使得两个控制栅极耦合到浮动栅极。可以通过等离子体氮化形成固定电荷层。

15. 发明授权

US08207036B2 Method for forming self-aligned dielectric cap above floating gate 有权
标题翻译：在浮动栅上形成自对准电介质盖的方法
公开(公告)号：US08207036B2
公开(公告)日：2012-06-26
申请号：US12242857
申请日：2008-09-30
申请人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , Henry Chien , James K. Kai
发明人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , Henry Chien , James K. Kai
IPC分类号： H01L21/336 , H01L21/8238 , H01L21/3205 , H01L21/4763 , H01L29/788
CPC分类号： H01L21/28273 , H01L27/11519 , H01L27/11521 , H01L29/513 , H01L29/7881
摘要： A method for fabricating a non-volatile storage element. The method comprises forming a layer of polysilicon floating gate material over a substrate and forming a layer of nitride at the surface of the polysilicon floating gate material. Floating gates are formed from the polysilicon floating gate material. Individual dielectric caps are formed from the nitride such that each individual nitride dielectric cap is self-aligned with one of the plurality of floating gates. An inter-gate dielectric layer is formed over the surface of the dielectric caps and the sides of the floating gates. Control gates are then formed with the inter-gate dielectric layer separating the control gates from the floating gates. The layer of nitride may be formed using SPA (slot plane antenna) nitridation. The layer of nitride may be formed prior to or after etching of the polysilicon floating gate material to form floating gates.
摘要翻译：一种用于制造非易失性存储元件的方法。该方法包括在衬底上形成多晶硅浮栅材料层，并在多晶硅浮栅材料的表面形成一层氮化物。浮栅由多晶硅浮栅材料形成。各个绝缘盖由氮化物形成，使得每个单独的氮化物介电帽与多个浮动栅之一自对准。在电介质盖的表面和浮动栅极的侧面上形成栅极间介电层。然后，栅极介电层与控制栅极与浮动栅极分离形成控制栅极。可以使用SPA（槽平面天线）氮化形成氮化物层。可以在蚀刻多晶硅浮栅材料之前或之后形成氮化物层以形成浮栅。

16. 发明授权

US08105867B2 Self-aligned three-dimensional non-volatile memory fabrication 有权
标题翻译：自对准三维非易失性存储器制造
公开(公告)号：US08105867B2
公开(公告)日：2012-01-31
申请号：US12468717
申请日：2009-05-19
申请人： George Matamis , Henry Chien , James K Kai , Takashi Orimoto , Vinod R Purayath , Er-Xuan Ping , Roy E Scheuerlein
发明人： George Matamis , Henry Chien , James K Kai , Takashi Orimoto , Vinod R Purayath , Er-Xuan Ping , Roy E Scheuerlein
IPC分类号： H01L21/00
CPC分类号： H01L21/20 , G11C13/0004 , G11C17/16 , G11C2213/71 , G11C2213/72 , H01L27/101 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1675
摘要： A self-aligned fabrication process for three-dimensional non-volatile memory is disclosed. A double etch process forms conductors at a given level in self-alignment with memory pillars both underlying and overlying the conductors. Forming the conductors in this manner can include etching a first conductor layer using a first repeating pattern in a given direction to form a first portion of the conductors. Etching with the first pattern also defines two opposing sidewalls of an underlying pillar structure, thereby self-aligning the conductors with the pillars. After etching, a second conductor layer is deposited followed by a semiconductor layer stack. Etching with a second pattern that repeats in the same direction as the first pattern is performed, thereby forming a second portion of the conductors that is self-aligned with overlying layer stack lines. These layer stack lines are then etched orthogonally to define a second set of pillars overlying the conductors.
摘要翻译：公开了一种用于三维非易失性存储器的自对准制造工艺。双重蚀刻工艺在与导体下面和上面的记忆柱自对准的给定水平处形成导体。以这种方式形成导体可以包括使用沿给定方向的第一重复图案蚀刻第一导体层以形成导体的第一部分。具有第一图案的蚀刻还限定了下面的柱结构的两个相对的侧壁，从而使导体与支柱自对准。蚀刻后，沉积第二导体层，随后沉积半导体层堆叠。执行以与第一图案相同的方向重复的第二图案的蚀刻，从而形成与上层叠层线自对准的导体的第二部分。然后将这些层堆叠线正交蚀刻以限定覆盖导体的第二组支柱。

17. 发明申请

US20100124813A1 Self-Aligned Three-Dimensional Non-Volatile Memory Fabrication 有权
标题翻译：自对准三维非易失性存储器制造
公开(公告)号：US20100124813A1
公开(公告)日：2010-05-20
申请号：US12468717
申请日：2009-05-19
申请人： George Matamis , Henry Chien , James K. Kai , Takashi Orimoto , Vinod R Purayath , Er-Xuan Ping , Roy E. Scheuerlein
发明人： George Matamis , Henry Chien , James K. Kai , Takashi Orimoto , Vinod R Purayath , Er-Xuan Ping , Roy E. Scheuerlein
IPC分类号： H01L21/20 , H01L21/3205
CPC分类号： H01L21/20 , G11C13/0004 , G11C17/16 , G11C2213/71 , G11C2213/72 , H01L27/101 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1675
摘要： A self-aligned fabrication process for three-dimensional non-volatile memory is disclosed. A double etch process forms conductors at a given level in self-alignment with memory pillars both underlying and overlying the conductors. Forming the conductors in this manner can include etching a first conductor layer using a first repeating pattern in a given direction to form a first portion of the conductors. Etching with the first pattern also defines two opposing sidewalls of an underlying pillar structure, thereby self-aligning the conductors with the pillars. After etching, a second conductor layer is deposited followed by a semiconductor layer stack. Etching with a second pattern that repeats in the same direction as the first pattern is performed, thereby forming a second portion of the conductors that is self-aligned with overlying layer stack lines. These layer stack lines are then etched orthogonally to define a second set of pillars overlying the conductors.
摘要翻译：公开了一种用于三维非易失性存储器的自对准制造工艺。双重蚀刻工艺在与导体下面和上面的记忆柱自对准的给定水平处形成导体。以这种方式形成导体可以包括使用沿给定方向的第一重复图案蚀刻第一导体层以形成导体的第一部分。具有第一图案的蚀刻还限定了下面的柱结构的两个相对的侧壁，从而使导体与支柱自对准。蚀刻后，沉积第二导体层，随后沉积半导体层堆叠。执行以与第一图案相同的方向重复的第二图案的蚀刻，从而形成与上层叠层线自对准的导体的第二部分。然后将这些层堆叠线正交蚀刻以限定覆盖导体的第二组支柱。

18. 发明授权

US08383479B2 Integrated nanostructure-based non-volatile memory fabrication 有权
公开(公告)号：US08383479B2
公开(公告)日：2013-02-26
申请号：US12840081
申请日：2010-07-20
申请人： Vinod Robert Purayath , James K. Kai , Masaaki Higashitani , Takashi Orimoto , George Matamis , Henry Chien
发明人： Vinod Robert Purayath , James K. Kai , Masaaki Higashitani , Takashi Orimoto , George Matamis , Henry Chien
IPC分类号： H01L21/8247
CPC分类号： H01L21/76224 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L27/11526 , H01L27/11529 , H01L27/11536 , H01L27/11546 , H01L27/11573 , H01L29/788 , Y10S438/962 , Y10S977/774 , Y10S977/936
摘要： Nanostructure-based charge storage regions are included in non-volatile memory devices and integrated with the fabrication of select gates and peripheral circuitry. One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating.

19. 发明授权

US08097498B2 Damascene method of making a nonvolatile memory device 有权
公开(公告)号：US08097498B2
公开(公告)日：2012-01-17
申请号：US12693322
申请日：2010-01-25
申请人： Vinod Robert Purayath , George Matamis , James Kai , Takashi Orimoto
发明人： Vinod Robert Purayath , George Matamis , James Kai , Takashi Orimoto
IPC分类号： H01L21/20
CPC分类号： H01L27/101 , H01L27/1021
摘要： A method of making a device includes providing a first device level containing first semiconductor rails separated by first insulating features, forming a sacrificial layer over the first device level, patterning the sacrificial layer and the first semiconductor rails in the first device level to form a plurality of second rails extending in a second direction, wherein the plurality of second rails extend at least partially into the first device level and are separated from each other by rail shaped openings which extend at least partially into the first device level, forming second insulating features between the plurality of second rails, removing the sacrificial layer, and forming second semiconductor rails between the second insulating features in a second device level over the first device level. The first semiconductor rails extend in a first direction. The second semiconductor rails extend in the second direction different from the first direction.

20. 发明授权

US07807529B2 Lithographically space-defined charge storage regions in non-volatile memory 有权
标题翻译：非易失性存储器中的光刻空间定义电荷存储区域
公开(公告)号：US07807529B2
公开(公告)日：2010-10-05
申请号：US11960513
申请日：2007-12-19
申请人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai
发明人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： Lithographically-defined spacing is used to define feature sizes during fabrication of semiconductor-based memory devices. Sacrificial features are formed over a substrate at a specified pitch having a line size and a space size defined by a photolithography pattern. Charge storage regions for storage elements are formed in the spaces between adjacent sacrificial features using the lithographically-defined spacing to fix a gate length or dimension of the charge storage regions in a column direction. Unequal line and space sizes at the specified pitch can be used to form feature sizes at less than the minimally resolvable feature size associated with the photolithography process. Larger line sizes can improve line-edge roughness while decreasing the dimension of the charge storage regions in the column direction. Additional charge storage regions for the storage elements can be formed over the charge storage regions so defined, such as by depositing and etching a second charge storage layer to form second charge storage regions having a dimension in the column direction that is less than the gate length of the first charge storage regions.
摘要翻译：在制造基于半导体的存储器件期间，使用光刻定义的间距来定义特征尺寸。牺牲特征以具有由光刻图案限定的线尺寸和空间尺寸的指定间距在衬底上形成。用于存储元件的电荷存储区域使用光刻定义的间隔在相邻的牺牲特征之间的空间中形成，以将电荷存储区域的栅极长度或尺寸固定在列方向上。可以使用指定间距处的不等的线和空间尺寸来形成小于与光刻工艺相关联的最小可解析特征尺寸的特征尺寸。较大的线尺寸可以改善线边缘粗糙度，同时减小电荷存储区域在列方向上的尺寸。存储元件的附加电荷存储区域可以形成在如此限定的电荷存储区域上，例如通过沉积和蚀刻第二电荷存储层以形成具有小于栅极长度的列方向尺寸的第二电荷存储区域的第一电荷存储区域。

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