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11. 发明授权

US08006041B2 Prefetch processing apparatus, prefetch processing method, storage medium storing prefetch processing program 失效
标题翻译：预取处理装置，预取处理方法，存储预取处理程序的存储介质
公开(公告)号：US08006041B2
公开(公告)日：2011-08-23
申请号：US12042891
申请日：2008-03-05
申请人： Shuji Yamamura , Takashi Aoki
发明人： Shuji Yamamura , Takashi Aoki
IPC分类号： G06F12/00
CPC分类号： G06F9/3824 , G06F11/3419 , G06F12/0862 , G06F2201/865 , G06F2201/885
摘要： A prefetch processing apparatus includes a central-processing-unit monitor unit that monitors processing states of the central processing unit in association with time elapsed from start time of executing a program. A cache-miss-data address obtaining unit obtains cache-miss-data addresses in association with the time elapsed from the start time of executing the program, and a cycle determining unit determines a cycle of time required for executing the program. An identifying unit identifies a prefetch position in a cycle in which a prefetch-target address is to be prefetched by associating the cycle determined by the cycle determining unit with the cache-miss data addresses obtained by the cache-miss-data address obtaining unit. The prefetch-target address is an address of data on which prefetch processing is to be performed.
摘要翻译：预取处理装置包括中央处理单元监视单元，其与从执行程序的开始时间起经过的时间相关联地监视中央处理单元的处理状态。高速缓存未命中数据地址获取单元从执行程序的开始时刻起经过的时间结果获得高速缓存未命中数据地址，循环确定单元确定执行程序所需的时间周期。识别单元通过将由循环确定单元确定的周期与由高速缓存未命中数据地址获取单元获得的高速缓存未命中数据地址相关联来在预取取目标地址预取的周期中识别预取位置。预取目标地址是要执行预取处理的数据的地址。

12. 发明授权

US07907328B2 Circuit board, electro-optic device, and electronic apparatus 有权
标题翻译：电路板，电光设备和电子设备
公开(公告)号：US07907328B2
公开(公告)日：2011-03-15
申请号：US12495928
申请日：2009-07-01
申请人： Takashi Aoki
发明人： Takashi Aoki
IPC分类号： G02B26/00
CPC分类号： G02F1/136227 , G02F1/167
摘要： A circuit board includes a substrate; a plurality of scan lines disposed on the substrate, the scan lines extending in a first direction; a plurality of signal lines disposed on the substrate, the signal lines extending in a second direction intersecting the first direction; a plurality of transistors, each of which is electrically connected to corresponding one of the plurality of scan lines and corresponding one of the plurality of signal lines; an insulating layer that covers the plurality of scan lines, the plurality of signal lines, and the plurality of transistors; and a plurality of electrodes, each of which is electrically connected to corresponding one of the plurality of transistors. One opening is formed in the insulating layer for every electrode group, the electrode group being constituted by at least two adjacent electrodes among the plurality of electrodes, and each of the plurality of electrodes is electrically connected to the corresponding one of the transistors through the opening.
摘要翻译：电路板包括基板; 设置在所述基板上的多条扫描线，所述扫描线沿第一方向延伸; 设置在所述基板上的信号线，所述信号线沿与所述第一方向交叉的第二方向延伸; 多个晶体管，其中的每一个电连接到所述多条扫描线中的相应一条扫描线和所述多条信号线中的一条; 覆盖所述多条扫描线，所述多条信号线和所述多个晶体管的绝缘层; 以及多个电极，每个电极电连接到多个晶体管中的对应的一个晶体管。在每个电极组的绝缘层中形成一个开口，电极组由多个电极中的至少两个相邻电极构成，并且多个电极中的每一个通过开口电连接到相应的一个晶体管。

13. 发明授权

US07896328B2 Postprocessing device and image forming device 有权
标题翻译：后处理装置和图像形成装置
公开(公告)号：US07896328B2
公开(公告)日：2011-03-01
申请号：US12138155
申请日：2008-06-12
申请人： Michihiro Kawamura , Kenji Kawana , Takashi Aoki , Daisuke Nagasaka , Kazuhisa Makita
发明人： Michihiro Kawamura , Kenji Kawana , Takashi Aoki , Daisuke Nagasaka , Kazuhisa Makita
IPC分类号： B42C1/10 , B41L43/00 , B65H33/04
CPC分类号： G03G15/6538 , G03G2215/00827 , G03G2215/00877
摘要： A postprocessing unit of a postprocessing device performs a postprocess including a preset folding process at a set folding position, with respect to recording sheets. A setting unit of the postprocessing device sets an adjustment amount of the folding position on the basis of a target value of the folding position, a measured value of the folding position after the folding process, and sheet quality information of the recording sheets. An adjusting unit of the postprocessing device adjusts the folding position of the postprocessing unit on the basis of the adjustment amount set by the setting unit. An adjustment control unit of the postprocessing device controls the adjustment by the adjusting unit on the basis of the adjustment amount set by the setting unit.
摘要翻译：后处理装置的后处理单元相对于记录纸执行包括在设定折叠位置的预设折叠处理的后处理。后处理装置的设定单元基于折叠位置的目标值，折叠处理后的折叠位置的测量值和记录片材的片材质量信息来设定折叠位置的调整量。后处理装置的调整单元根据由设定单元设定的调整量来调整后处理单元的折叠位置。后处理装置的调整控制单元基于由设定单元设定的调整量来控制调整单元的调整。

14. 发明授权

US07860227B2 Telephone exchange apparatus, telephone exchange system, and accounting method 有权
标题翻译：电话交换设备，电话交换系统和会计方法
公开(公告)号：US07860227B2
公开(公告)日：2010-12-28
申请号：US11473140
申请日：2006-06-23
申请人： Takashi Aoki
发明人： Takashi Aoki
IPC分类号： H04M15/00
CPC分类号： H04M15/00 , H04M15/41 , H04M2215/0164
摘要： If a call is originated from a DKT, a first node being a calling party prepares a call identifying information item using a call number and a Node ID, and transmits the information item to a second node being a called party. If the first node and the second node receive a disconnect request of the call from the DKT, each of the nodes transmits an accounting information item and the call identification item to an accounting apparatus. The accounting apparatus sums up accounting information items having the same call identification item, and performs accounting processing for the summed accounting information as total accounting information of the call.
摘要翻译：如果来自DKT的呼叫，作为主叫方的第一节点使用呼叫号码和节点ID准备呼叫识别信息项目，并将该信息项目发送到作为被叫方的第二节点。如果第一节点和第二节点从DKT接收到呼叫的断开请求，则每个节点将会计信息项和呼叫识别项发送到会计装置。会计装置对具有相同呼叫识别项目的会计信息项进行总结，并且对计算结算信息进行计费处理，作为呼叫总计费信息。

15. 发明申请

US20100316105A1 APPARATUS FOR MEASURING JITTER TRANSFER CHARACTERISTIC 有权
标题翻译：用于测量抖动传递特性的装置
公开(公告)号：US20100316105A1
公开(公告)日：2010-12-16
申请号：US12691376
申请日：2010-01-21
申请人： Seiya Suzuki , Takashi Aoki , Ken Mochizuki
发明人： Seiya Suzuki , Takashi Aoki , Ken Mochizuki
IPC分类号： H04B17/00
CPC分类号： G01R31/2837
摘要： An apparatus for rapidly measuring jitter transfer characteristics is provided. A modulation signal generator generates a modulation signal M including a plurality of sinusoidal components having known amplitudes m1 to mn and different frequencies f1 to fn, and outputs the modulation signal M to a jitter generator. A clock signal C phase-modulated by the modulation signal M is input to a data signal generator, a data signal D synchronized with the clock signal C is provided to a measurement object, a data signal D′ output from the measurement object is input to a clock recovery unit to recover a clock signal component C′, and the clock signal component C′ is phase-detected by a phase detector. A signal amplitude detector detects the amplitudes of the plurality of sinusoidal components included in the modulation signal M from an output signal M′ of the phase detector, and an operation processor calculates a ratio of the detected amplitudes and the known amplitudes for each of the sinusoidal components, respectively.
摘要翻译：提供了一种用于快速测量抖动传输特性的装置。调制信号发生器产生包括具有已知幅度m1至mn和不同频率f1至fn的多个正弦分量的调制信号M，并将调制信号M输出到抖动发生器。将通过调制信号M相位调制的时钟信号C输入到数据信号发生器，将与时钟信号C同步的数据信号D提供给测量对象，将从测量对象输出的数据信号D'输入到用于恢复时钟信号分量C'的时钟恢复单元，并且时钟信号分量C'被相位检测器相位检测。信号幅度检测器从相位检测器的输出信号M'检测包含在调制信号M中的多个正弦分量的振幅，并且操作处理器计算每个正弦曲线的检测振幅和已知幅度的比率组件。

16. 发明授权

US07841619B2 Interior component for a vehicle and method of mounting the same 有权
标题翻译：用于车辆的内部部件及其安装方法
公开(公告)号：US07841619B2
公开(公告)日：2010-11-30
申请号：US12205140
申请日：2008-09-05
申请人： Kazuaki Miyamoto , Takashi Aoki , Shizuo Hosoya , Takashi Nakamura , Hiroyuki Isayama , Koji Ikeda , Masayuki Kaneko , Nobumoto Sekiguchi
发明人： Kazuaki Miyamoto , Takashi Aoki , Shizuo Hosoya , Takashi Nakamura , Hiroyuki Isayama , Koji Ikeda , Masayuki Kaneko , Nobumoto Sekiguchi
IPC分类号： B60R21/20
CPC分类号： B62D39/00
摘要： An interior component for a vehicle formed by superimposing a bottom edge portion of a second interior component on a top edge portion of a first interior component or by placing these portions so as to face against each other, and by joining these interior components together by a joining component, wherein the joining component includes: a top supporting portion joined to a back surface of the second interior component, which supports a top edge side of the second interior component; and a bottom engaging portion provided underneath of and separated from the top supporting portion, which engages the bottom edge of the second interior component with the first interior component.
摘要翻译：一种用于车辆的内部部件，其通过将第二内部部件的底部边缘部分叠加在第一内部部件的顶部边缘部分上，或者通过将这些部分相对于彼此面对并通过将这些内部部件连接在一起而形成接合部件，其中所述接合部件包括：顶部支撑部分，其接合到所述第二内部部件的后表面，所述顶部支撑部分支撑所述第二内部部件的顶部边缘侧; 以及底部接合部分，其设置在所述顶部支撑部分的下方并与所述顶部支撑部分分离，所述底部接合部分与所述第一内部部件接合所述第二内部部件的底部边缘。

17. 发明申请

US20100171129A1 ACTIVE MATRIX SUBSTRATE, ELECTROPHORETIC DISPLAY APPARATUS, AND ELECTRONIC DEVICE 有权
标题翻译：有源矩阵基板，电子显示设备和电子设备
公开(公告)号：US20100171129A1
公开(公告)日：2010-07-08
申请号：US12648418
申请日：2009-12-29
申请人： Takashi Aoki , Kazuya Nakamura
发明人： Takashi Aoki , Kazuya Nakamura
IPC分类号： H01L33/00
CPC分类号： G02F1/167 , G02F1/136213 , G09G3/344 , G09G2300/0809 , G09G2300/0876 , G09G2310/0262 , G09G2320/0252 , H01L27/3274
摘要： An active matrix substrate includes a substrate; a plurality of data lines provided on the substrate; a plurality of scanning lines provided to cross the data lines on the substrate when seen in a plan view; a thin film transistor that is electrically connected to one of the plurality of data lines and one of the plurality of scanning lines and has an organic semiconductor layer; a pixel electrode electrically connected to the thin film transistor; and a capacitive element electrically connected in parallel with the thin film transistor between the data line and the pixel electrode.
摘要翻译：有源矩阵基板包括基板; 设置在所述基板上的多条数据线; 多个扫描线设置成在平面图中观察时跨越基板上的数据线; 电连接到所述多条数据线之一和所述多条扫描线中的一条并具有有机半导体层的薄膜晶体管; 电连接到所述薄膜晶体管的像素电极; 以及与数据线和像素电极之间的薄膜晶体管并联电连接的电容元件。

18. 发明申请

US20100095102A1 INDIRECT BRANCH PROCESSING PROGRAM AND INDIRECT BRANCH PROCESSING METHOD 审中-公开
标题翻译：间接分支处理程序和间接分支处理方法
公开(公告)号：US20100095102A1
公开(公告)日：2010-04-15
申请号：US12641027
申请日：2009-12-17
申请人： Takashi Toyoshima , Takashi Aoki
发明人： Takashi Toyoshima , Takashi Aoki
IPC分类号： G06F9/38
CPC分类号： G06F9/3844 , G06F8/4442 , G06F9/322 , G06F9/3806
摘要： A processor reads an interpreter program to start an interpreter. The interpreter makes branch prediction by executing, in place of an indirect branch instruction that is necessary for execution of a source program, storing branch destination addresses in the indirect branch instruction in a link register (the processor internally stacks the branch destination addresses also in a return address stack) in inverse order and reading the addresses from the return address stack in one at a time manner.
摘要翻译：处理器读取解释程序以启动解释器。解释器通过执行代替执行源程序所必需的间接分支指令来进行分支预测，将分支目的地址存储在链接寄存器中的间接分支指令中（处理器也将分支目的地地址也在返回地址堆栈），并以一种方式从返回地址堆栈中读取地址。

19. 发明授权

US07675732B2 Multilayer capacitor array 有权
标题翻译：多层电容阵列
公开(公告)号：US07675732B2
公开(公告)日：2010-03-09
申请号：US12051316
申请日：2008-03-19
申请人： Takashi Aoki
发明人： Takashi Aoki
IPC分类号： H01G4/005 , H01G4/30 , H01G4/228
CPC分类号： H01G4/012 , H01G4/232 , H01G4/30
摘要： A multilayer capacitor array includes a capacitor body having rectangular first and second main faces opposing each other. In the capacitor body having a dielectric characteristic, first inner electrodes are arranged in a first region, second inner electrodes are arranged in a second region, and third and fourth inner electrodes are arranged so as to extend over the first and second regions. Each of the third inner electrodes opposes at least one of the first inner electrodes and at least one of the second inner electrodes. Each of the fourth inner electrodes opposes at least one of the first inner electrodes and at least one of the second inner electrodes. The third inner electrodes are adjacent to the fourth inner electrodes, respectively.
摘要翻译：一种层叠电容器阵列包括具有彼此相对的矩形第一和第二主面的电容器本体。在具有介电特性的电容器主体中，第一内部电极配置在第一区域中，第二内部电极配置在第二区域中，第三和第四内部电极被布置成在第一和第二区域上延伸。第三内电极中的每一个与第一内电极和第二内电极中的至少一个相对。第四内电极中的每一个与第一内电极和第二内电极中的至少一个相对。第三内电极分别与第四内电极相邻。

20. 发明授权

US07667978B2 Electronic package encapsulating electronic components therein 有权
标题翻译：在其中封装电子部件的电子封装
公开(公告)号：US07667978B2
公开(公告)日：2010-02-23
申请号：US11826552
申请日：2007-07-17
申请人： Shinsuke Nagasaka , Kazuo Katoh , Akira Shintai , Takashi Aoki
发明人： Shinsuke Nagasaka , Kazuo Katoh , Akira Shintai , Takashi Aoki
IPC分类号： H01R7/00
CPC分类号： H01L23/3142 , H01L23/3107 , H01L24/32 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/8592 , H01L2924/181 , H01L2924/19041 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： An electronic component unit including a metallic member and an electronic component, such as a semiconductor element, mounted on the metallic member is encapsulated with molding resin such as epoxy resin, thereby forming an electronic package. The electronic component unit is covered with primer made of a material such as resin to increase an adhesive force of the molding resin to the electronic component unit. A glass transition temperature of both of the molding resin and the primer is set to a temperature higher than 200° C. to keep the adhesive force unchanged at least up to the ambient temperature of 200° C. and to secure a reliability of the electronic package. A metallic lead wire connected to the electronic component may be encapsulated together with the electronic component unit. An entire surface of the electronic component unit may be covered with the primer to further improve the adhesive force.
摘要翻译：包括金属构件和安装在金属构件上的诸如半导体元件的电子部件的电子部件单元用诸如环氧树脂的模塑树脂封装，从而形成电子封装。电子部件单元被由诸如树脂的材料制成的底漆覆盖以增加模制树脂对电子部件单元的粘合力。将模塑树脂和底漆两者的玻璃化转变温度设定为高于200℃的温度，以保持粘合力至少不超过200℃的环境温度，并确保电子的可靠性包。连接到电子部件的金属引线可以与电子部件单元一起封装。电子部件单元的整个表面可以被底漆覆盖，以进一步提高粘合力。

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