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11. 发明授权

US07700937B2 Single-photon generating device, single-photon detecting device, and optical quantum gate 有权
标题翻译：单光子发生装置，单光子检测装置和光量子门
公开(公告)号：US07700937B2
公开(公告)日：2010-04-20
申请号：US11522421
申请日：2006-09-18
申请人： Shinichi Hirose , Motomu Takatsu , Tatsuya Usuki , Yasuhiko Arakawa
发明人： Shinichi Hirose , Motomu Takatsu , Tatsuya Usuki , Yasuhiko Arakawa
IPC分类号： H01L33/00
CPC分类号： H01L31/035281 , H01L31/02327 , H01L31/03046 , H01L33/20 , H01S5/0201 , Y02E10/50 , Y10S977/949 , Y10S977/95
摘要： A single-photon generating device is configured to have a solid substrate including abase portion, and a pillar portion which is formed on the surface side of the base portion with a localized level existent in the vicinity of the tip of the base portion. The above pillar portion is formed to have a larger cross section on the base portion side than the cross section on the tip side, so that the light generated from the localized level is reflected on the surface, propagated inside the pillar portion, and output from the back face side of the base portion.
摘要翻译：单光子产生装置被配置为具有包括基部的固体基板，并且在基部的尖端附近存在形成有位于基部的表面侧的柱部。上述柱部形成为在基部侧的截面比前端侧的截面大的截面，使得从局部水平产生的光在表面上反射，在柱部内传播，并从基部的背面侧。

12. 发明授权

US6070183A Arithmetic unit, correlation arithmetic unit and dynamic image compression apparatus 失效
标题翻译：算术单元，相关运算单元和动态图像压缩装置
公开(公告)号：US6070183A
公开(公告)日：2000-05-30
申请号：US236474
申请日：1999-01-25
申请人： Susumu Kawakami , Hiroaki Okamoto , Motomu Takatsu
发明人： Susumu Kawakami , Hiroaki Okamoto , Motomu Takatsu
IPC分类号： G06F7/50 , G06F17/15 , G06G7/12 , G06K9/36 , G06K9/64 , H04N19/42 , H04N19/46 , H04N19/50 , H04N19/51 , H04N19/597 , H04N19/60 , H04N19/70
CPC分类号： G06F17/15
摘要： In a correlation arithmetic system adapted to detect a relative difference between two functions, an operation is simplified. This makes it possible to perform the operation with a small scale of hardware and also with great accuracy. There is adopted an operation g*h instead of the "product" in the correlation arithmetic operation. There is disclosed an arithmetic unit in which two numeral values a and b are inputted, and the two numerical values a and b are subjected to a predetermined operation process, so that a numerical value c representative of an operation result is derived. The arithmetic unit has an absolute value operation unit for evaluating an absolute value .vertline.c.vertline. of the numerical value c, and a sign operation unit for evaluating a sign "sign (c)" of the numerical value c.
摘要翻译：在适于检测两个功能之间的相对差异的相关运算系统中，简化了操作。这使得可以以小规模的硬件并且以很高的精度执行操作。在相关算术运算中采用运算g * h而不是“乘积”。公开了一种算术单元，其中输入了两个数值+ E，uns a + EE和+ E，uns b + EE，并且两个数值+ E，uns a + EE和+ E，uns b + EE 进行预定的操作处理，从而导出代表操作结果的数值+ E，uns c + EE。算术单元具有用于评估绝对值| c |的绝对值运算单元的数值+ E，uns c + EE和用于评估数值+ E，uns c + EE的符号“sign（c）”的符号操作单元。

13. 发明授权

US5917732A Arithmetic unit, correlation arithmetic unit and dynamic image compression apparatus 失效
公开(公告)号：US5917732A
公开(公告)日：1999-06-29
申请号：US724961
申请日：1996-09-05
申请人： Susumu Kawakami , Hiroaki Okamoto , Motomu Takatsu
发明人： Susumu Kawakami , Hiroaki Okamoto , Motomu Takatsu
IPC分类号： G06F7/50 , G06F17/15 , G06G7/12 , G06K9/36 , G06K9/64 , H04N19/42 , H04N19/46 , H04N19/50 , H04N19/51 , H04N19/597 , H04N19/60 , H04N19/70 , G06F7/38
CPC分类号： G06F17/15
摘要： In a correlation arithmetic system adapted to detect a relative difference between two functions, an operation is simplified. This makes it possible to perform the operation with a small scale of hardware and also with great accuracy. There is adopted an operation g*h instead of the "product" in the correlation arithmetic operation. There is disclosed an arithmetic unit in which two numeral values a and b are inputted, and the two numerical values a and b are subjected to a predetermined operation process, so that a numerical value c representative of an operation result is derived. The arithmetic unit has an absolute value operation unit for evaluating an absolute value .vertline.c.vertline. of the numerical value c, and a sign operation unit for evaluating a sign "sign (c)" of the numerical value c.

14. 发明授权

US07421017B2 Digital filter adaptively learning filter coefficient 失效
标题翻译：数字滤波器自适应学习滤波系数
公开(公告)号：US07421017B2
公开(公告)日：2008-09-02
申请号：US10639616
申请日：2003-08-12
申请人： Motomu Takatsu
发明人： Motomu Takatsu
IPC分类号： H03K5/159 , H04B1/10
CPC分类号： H03H21/0012 , H03H2021/0096
摘要： A linear filter feeds back an error signal generated using the output of an adaptive filter to a learning circuit. The learning circuit learns the coefficients of the adaptive filter using the error signal. The coefficients of the linear filter are determined depending on the generation method of a target signal for error minimization. In a signal interpolation type timing recovery digital filter, the coefficients of an inverse interpolation filter are determined in such a way as to minimize an error of a signal after interpolation.
摘要翻译：线性滤波器将自适应滤波器的输出产生的误差信号反馈给学习电路。学习电路使用误差信号学习自适应滤波器的系数。根据用于误差最小化的目标信号的生成方法确定线性滤波器的系数。在信号内插型定时恢复数字滤波器中，以内插后的信号的误差最小化的方式确定逆内插滤波器的系数。

15. 发明授权

US6032167A Data processing circuit adapted for use in pattern matching 失效
标题翻译：适用于模式匹配的数据处理电路
公开(公告)号：US6032167A
公开(公告)日：2000-02-29
申请号：US44973
申请日：1998-03-20
申请人： Motomu Takatsu
发明人： Motomu Takatsu
IPC分类号： G06T7/40 , G06F17/10 , G06T7/20 , G06T7/60 , G06F15/00
CPC分类号： G06T7/206
摘要： A data processing circuit adapted for use in pattern matching between two sets of multi-dimensional signal data. The data processing circuit performs integration-based conversion on data aw calculated by multiplying first multi-dimensional signal data a by a window function w, second multi-dimensional signal data b, data b.sup.2 calculated by squaring the data b, and the window function w, calculates a correlation between the first and second multi-dimensional signal data items a and b on the basis of the data aw and data b subjected to integration-based conversion, calculates a means of deviations from the square of the second multi-dimensional signal data b on the basis of the data b.sup.2 and window function subjected to integration-based conversion, and calculates a portion of the second multi-dimensional signal data b most consistent with the first multi-dimensional signal data a multiplied by the window function w. Owing to this processing, a motion vector (magnitude of movement) can be detected by carrying out a small number of arithmetic operations while hardly being affected by the variation of a signal representing the multi-dimensional signal data used for comparison. This contributes to high-precision pattern matching.
摘要翻译：一种数据处理电路，适用于两组多维信号数据之间的模式匹配。数据处理电路对通过将第一多维信号数据a乘以窗函数w，第二多维信号数据b，通过平方数据b计算出的数据b2和窗函数w来计算的数据aw执行基于积分的转换基于经过基于积分的转换的数据aw和数据b计算第一和第二多维信号数据项a和b之间的相关性，计算与第二多维信号的平方的偏差的平均值数据b基于经过基于积分的转换的数据b2和窗口函数，并且计算与第一多维信号数据a最相符的第二多维信号数据b的一部分乘以窗函数w。由于这种处理，通过执行少量的算术运算，可以检测运动矢量（运动的大小），同时几乎不受表示用于比较的多维信号数据的信号的变化的影响。这有助于高精度模式匹配。

16. 发明授权

US5426682A Sequential logic circuit having state hold circuits 失效
标题翻译：具有状态保持电路的顺序逻辑电路
公开(公告)号：US5426682A
公开(公告)日：1995-06-20
申请号：US797936
申请日：1991-11-26
申请人： Motomu Takatsu
发明人： Motomu Takatsu
IPC分类号： G06F7/00 , G05B19/07 , G11C19/28 , H03K3/36 , H03K19/21 , H03K23/54 , G11C19/00
CPC分类号： H03K3/36 , G05B19/07 , H03K19/212
摘要： A sequential logic circuit includes N state hold circuit where N is an integer. Each of the state hold circuits has a first input terminal, a second input terminal and an output terminal. The state hold circuits are cascaded via the respective first input terminals. The second input terminals of the state hold circuits receive a first clock signal. The first input terminal of one of the state hold circuits in a first stage receives a data signal. The output signal is obtained via the output terminal of one of the state hold circuits in a final stage. Each of the state hold circuits has the following truth table:______________________________________ A B Qn + 1 ______________________________________ 0 0 1 or 0 0 1 Qn 1 0 Qn 1 1 0 or 1 ______________________________________ wherein A and B designate the respective logic level signals applied to the first and second input terminals and Qn+1 designates the respective logic level of the resultant, current output signal produced at the output terminal in response to the corresponding, current logic levels input signals A and B, Qn representing that the prior logic level output signal is maintained as the current logic level output signal.
摘要翻译：顺序逻辑电路包括N状态保持电路，其中N是整数。每个状态保持电路具有第一输入端，第二输入端和输出端。状态保持电路经由各自的第一输入端子级联。状态保持电路的第二输入端接收第一时钟信号。第一级的状态保持电路之一的第一输入端接收数据信号。输出信号通过最后一级状态保持电路之一的输出端获得。每个状态保持电路具有以下真值表：-AB Qn + 1 -0 0 1或0 -0 1 Qn -1 0 Qn -1 1 0或1 - 其中A和B表示施加到第一和第二输入端和Qn + 1表示响应于对应的当前逻辑电平输入信号A和B的输出端产生的所得到的当前输出信号的相应逻辑电平，Qn表示先前的逻辑电平输出信号保持为当前逻辑电平输出信号。

17. 发明授权

US5260609A Logic circuit uising transistor having negative differential conductance 失效
标题翻译：使用具有负微分电导的晶体管的逻辑电路
公开(公告)号：US5260609A
公开(公告)日：1993-11-09
申请号：US945591
申请日：1992-09-16
申请人： Motomu Takatsu
发明人： Motomu Takatsu
IPC分类号： H01L27/06 , H03K3/36 , H03K19/08 , H03K19/21 , H03K19/013 , H03K4/787
CPC分类号： H03K3/36 , H01L27/0605 , H03K19/08 , H03K19/212
摘要： A logic circuit first, second and third input terminals, an output terminal, a load resistance element, and a transistor having a negative differential conductance. The collector is connected to the output terminal and coupled to a first power source via the load resistance element. The emitter is connected to a second power source. First, second and third resistors are connected between the base of the transistor and the first, second and third input terminals, respectively. A fourth resistor is connected between the base and emitter of the transistor. The resistance values of the first, second, third and fourth resistors are selected so that the transistor has first and second operating points respectively obtained when all the first, second and third input terminals are at a low level and when two of the first, second and third input terminals are at a high level, and has third and fourth operating points respectively obtained when one of the first, second and third input terminals is at the high level and when all the first, second and third input terminals are at the high level. A collector current obtained at the first and second operating points is less than that obtained at the third and fourth operating points.
摘要翻译：逻辑电路第一，第二和第三输入端子，输出端子，负载电阻元件和具有负微分电导的晶体管。集电极连接到输出端并通过负载电阻元件耦合到第一电源。发射极连接到第二个电源。首先，第二和第三电阻分别连接在晶体管的基极与第一，第二和第三输入端之间。第四电阻连接在晶体管的基极和发射极之间。选择第一，第二，第三和第四电阻器的电阻值，使得晶体管具有在所有第一，第二和第三输入端子处于低电平时分别获得的第一和第二工作点，以及当第一，第二，第二电阻并且第三输入端子处于高电平，并且当第一，第二和第三输入端子之一处于高电平时，并且当所有第一，第二和第三输入端子处于高电平时，分别具有第三和第四工作点水平。在第一和第二操作点获得的集电极电流小于在第三和第四操作点获得的集电极电流。

18. 发明授权

US08280044B2 Stream encryption method and encryption system 失效
标题翻译：流加密方式和加密系统
公开(公告)号：US08280044B2
公开(公告)日：2012-10-02
申请号：US12492841
申请日：2009-06-26
申请人： Motomu Takatsu
发明人： Motomu Takatsu
IPC分类号： H04L9/00
CPC分类号： H04L9/0656 , H04L9/002
摘要： A stream encryption method encodes plaintext of N number of 1-bit input signal sequences into L (L is N or more) bits of encrypted text using N number of pseudo random sequences and uses only one pseudo random sequence used for the encryption to decode the single corresponding plaintext. This stream encryption method comprises using the N number of pseudo random sequences to divide a L-bit encryption symbol set averagely into two equal parts; selecting either of the two partial sets by a corresponding 1-bit plaintext sequence; and when there are one or more elements of the selected N number of partial sets forming common parts in the sets, using one of those as an encryption symbol.
摘要翻译：流加密方法使用N个伪随机序列将N个1位输入信号序列的明文编码成L（L是N个或更多）个加密文本位，并且仅使用用于加密的一个伪随机序列来解码单一对应明文。该流加密方法包括使用N个伪随机序列将L位加密符号集合平均分成两部分; 通过相应的1位明文序列选择两个部分集合中的任一个; 并且当所选择的N个部分集合中的一个或多个元素在集合中形成公共部分时，使用其中的一个作为加密符号。

19. 发明授权

US06430319B1 Data conversion processing circuit 失效
标题翻译：数据转换处理电路
公开(公告)号：US06430319B1
公开(公告)日：2002-08-06
申请号：US09037884
申请日：1998-03-10
申请人： Motomu Takatsu
发明人： Motomu Takatsu
IPC分类号： G06K936
CPC分类号： G06K9/4633
摘要： A data conversion processing circuit which effects processing for data conversion which projects two-dimensional data on a plurality of straight lines with different inclinations. The data conversion processing circuit includes a circuit unit for storing two-dimensional data, a circuit unit for producing x and y coordinate locating data, which serves as an addend, according to an angle &thgr; and generating a signal for use in selecting data, a circuit unit for selecting data, which serves as an addend, from among stored data in response to the control signal, and a circuit unit for adding selected data. For producing coordinates and selecting data, the data conversion processing circuit carries out arithmetic operations for a Hough transform expressed as AH(&rgr;, &thgr;)=∫a(&rgr;·cos &thgr;−t·sin &thgr;, &rgr;·sin &thgr;+t·cos &thgr;)dt. For handling different angles &thgr;, the arithmetic operations are carried out in a time-division manner. Owing to the configuration, a Hough transform can be achieved by performing a small number of arithmetic operations. This contributes to an increase in the processing speed.
摘要翻译：一种数据转换处理电路，用于对具有不同倾斜度的多条直线投影二维数据的数据转换处理。数据转换处理电路包括用于存储二维数据的电路单元，用于产生x和y坐标定位数据的电路单元，其用作加数，根据角度θ并产生用于选择数据的信号，电路单元，用于响应于控制信号从存储的数据中选择用作加数的数据，以及用于添加所选数据的电路单元。为了产生坐标和选择数据，数据转换处理电路对表示为AH（rho，θ）=∫a（rho.cosθ-t.sinθ，rho.sinθ+ t.cos）的霍夫变换执行算术运算 theta）dt。为了处理不同的角度θ，算术运算以时分方式进行。由于该配置，可以通过执行少量的算术运算来实现霍夫变换。这有助于提高处理速度。

20. 发明授权

US6101518A Arithmetic unit, correlation arithmetic unit and dynamic image compression apparatus 失效
标题翻译：算术单元，相关运算单元和动态图像压缩装置
公开(公告)号：US6101518A
公开(公告)日：2000-08-08
申请号：US236365
申请日：1999-01-25
申请人： Susumu Kawakami , Hiroaki Okamoto , Motomu Takatsu
发明人： Susumu Kawakami , Hiroaki Okamoto , Motomu Takatsu
IPC分类号： G06F7/50 , G06F17/15 , G06G7/12 , G06K9/36 , G06K9/64 , H04N19/42 , H04N19/46 , H04N19/50 , H04N19/51 , H04N19/597 , H04N19/60 , H04N19/70
CPC分类号： G06F17/15
摘要： In a correlation arithmetic system adapted to detect a relative difference between two functions, an operation is simplified. This makes it possible to perform the operation with a small scale of hardware and also with great accuracy. There is adopted an operation g*h instead of the "product" in the correlation arithmetic operation. There is disclosed an arithmetic unit in which two numeral values a and b are inputted, and the two numerical values a and b are subjected to a predetermined operation process, so that a numerical value c representative of an operation result is derived. The arithmetic unit has an absolute value operation unit for evaluating an absolute value .vertline.c.vertline. of the numerical value c, and a sign operation unit for evaluating a sign "sing (c)" of the numerical value c.
摘要翻译：在适于检测两个功能之间的相对差异的相关运算系统中，简化了操作。这使得可以以小规模的硬件并且以很高的精度执行操作。在相关算术运算中采用运算g * h而不是“乘积”。公开了一种算术单元，其中输入了两个数值+ E，uns a + EE和+ E，uns b + EE，并且两个数值+ E，uns a + EE和+ E，uns b + EE 进行预定的操作处理，从而导出代表操作结果的数值+ E，uns c + EE。算术单元具有用于评估绝对值| c |的绝对值运算单元数值+ E，uns c + EE和用于评估数值+ E，uns c + EE的符号“sing（c）”的符号操作单元。

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