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11. 发明授权

US5523602A Multi-layered structure having single crystalline semiconductor film formed on insulator 失效
标题翻译：具有形成在绝缘体上的单晶半导体膜的多层结构
公开(公告)号：US5523602A
公开(公告)日：1996-06-04
申请号：US291652
申请日：1994-08-16
申请人： Masatada Horiuchi , Takahiro Onai , Katsuyoshi Washio
发明人： Masatada Horiuchi , Takahiro Onai , Katsuyoshi Washio
IPC分类号： H01L21/762 , H01L21/02 , H01L21/304 , H01L21/8249 , H01L27/06 , H01L27/12 , H01L29/786 , H01L27/01
CPC分类号： H01L27/1203
摘要： Disclosed is an multi-layered SOI substrate, which includes a supporting substrate, and a first insulator, a semiconductor film, a second insulator and a single crystalline semiconductor film (SOI film) which are layered on the main surface of the supporting substrate. The SOI substrate is formed by a direct bonding technique, and a bipolar transistor and an MOS transistor are formed using the single crystalline semiconductor film (SOI layer). The extremely shallow junction can be formed without epitaxial growth, thereby significantly increasing the operation speed of the semiconductor device at a low cost.
摘要翻译：公开了一种多层SOI衬底，其包括支撑衬底和层叠在支撑衬底的主表面上的第一绝缘体，半导体膜，第二绝缘体和单晶半导体膜（SOI膜）。 SOI衬底通过直接接合技术形成，并且使用单晶半导体膜（SOI层）形成双极晶体管和MOS晶体管。可以在没有外延生长的情况下形成极浅的结，从而以低成本显着提高半导体器件的操作速度。

12. 发明授权

US06936875B2 Insulated-gate field-effect transistor, method of fabricating same, and semiconductor device employing same 有权
标题翻译：绝缘栅场效应晶体管，其制造方法以及采用该绝缘栅场效应晶体管的半导体器件
公开(公告)号：US06936875B2
公开(公告)日：2005-08-30
申请号：US10673789
申请日：2003-09-30
申请人： Nobuyuki Sugii , Kazuhiro Ohnishi , Katsuyoshi Washio
发明人： Nobuyuki Sugii , Kazuhiro Ohnishi , Katsuyoshi Washio
IPC分类号： H01L21/764 , H01L21/02 , H01L21/20 , H01L21/336 , H01L21/762 , H01L21/8234 , H01L27/08 , H01L27/088 , H01L27/12 , H01L29/10 , H01L29/786 , H01L29/80
CPC分类号： H01L29/785 , H01L29/1054 , H01L29/66795 , H01L29/7842 , H01L29/78648 , H01L29/78687 , H01L29/802
摘要： With the invention, it is possible to avoid deterioration in short-channel characteristics, caused by a silicon germanium layer coming into contact with the channel of a strained SOI transistor. Further, it is possible to fabricate a double-gate type of strained SOI transistor or to implement mixedly mounting the strained SOI transistor and a conventional silicon or SOI transistor on the same wafer. According to the invention, for example, a strained silicon layer is grown on a strain-relaxed silicon germanium layer, and subsequently, portions of the silicon germanium layer are removed, thereby constituting a channel layer in the strained silicon layer.
摘要翻译：利用本发明，可以避免由与应变SOI晶体管的沟道接触的硅锗层引起的短沟道特性的劣化。此外，可以制造双栅型应变SOI晶体管，或者在同一晶片上实现将应变SOI晶体管和常规硅或SOI晶体管混合安装。根据本发明，例如，在应变松弛硅锗层上生长应变硅层，随后去除硅锗层的部分，从而在应变硅层中构成沟道层。

13. 发明授权

US4949151A Bipolar transistor having side wall base and collector contacts 失效
标题翻译：具有侧壁基极和集电极触点的双极晶体管
公开(公告)号：US4949151A
公开(公告)日：1990-08-14
申请号：US100232
申请日：1987-09-23
申请人： Masatada Horiuchi , Katsuyoshi Washio , Tohru Nakamura
发明人： Masatada Horiuchi , Katsuyoshi Washio , Tohru Nakamura
IPC分类号： H01L21/331 , H01L21/74 , H01L23/485 , H01L27/082 , H01L29/08 , H01L29/417 , H01L29/423 , H01L29/45
CPC分类号： H01L29/66272 , H01L21/743 , H01L23/485 , H01L27/0823 , H01L29/0821 , H01L29/41708 , H01L29/42304 , H01L29/456 , H01L2924/0002
摘要： A high integration bipolar transistor operable at very high operating speed is disclosed. A semiconductor device of this invention has a semiconductor substrate of a first conductivity type, a buried impurity region formed on the substrate, and a bipolar transistor formed on the buried impurity region, wherein a plurality of monocrystalline active regions defined by the buried impurity region are isolated from each other by an element isolation insulator, the buried impurity region is connected to a graft region formed on the element isolation insulator at least at the side wall of the buried impurity region, and connected to a semiconductor element in a different active region via the graft region.
摘要翻译：公开了以非常高的工作速度工作的高集成度双极晶体管。本发明的半导体器件具有第一导电类型的半导体衬底，形成在衬底上的掩埋杂质区域和形成在掩埋杂质区域上的双极晶体管，其中由掩埋杂质区域限定的多个单晶有源区域是通过元件隔离绝缘体彼此隔离，所述掩埋杂质区至少在所述掩埋杂质区的侧壁处连接到形成在所述元件隔离绝缘体上的移植区域，并且经由所述掩模杂质区域连接到不同有源区域中的半导体元件移植区域。

14. 发明授权

US4887145A Semiconductor device in which electrodes are formed in a self-aligned manner 失效
标题翻译：电极以自对准方式形成的半导体器件
公开(公告)号：US4887145A
公开(公告)日：1989-12-12
申请号：US937610
申请日：1986-12-03
申请人： Katsuyoshi Washio , Tohru Nakamura , Kazuo Nakazato , Masatada Horiuchi , Tetsuya Hayashida
发明人： Katsuyoshi Washio , Tohru Nakamura , Kazuo Nakazato , Masatada Horiuchi , Tetsuya Hayashida
IPC分类号： H01L21/285 , H01L21/32 , H01L21/331 , H01L29/423 , H01L29/732 , H01L29/04
CPC分类号： H01L29/66272 , H01L21/28525 , H01L21/32 , H01L29/42304 , H01L29/7325
摘要： A bipolar transistor capable of operating at high speeds. In a bipolar transistor designed for operation at high speeds, a polycrystalline silicon layer used as a base electrode effects is a contact area with respect to the base region which lacks precision or tends to increase. Further, when the transistor is formed in a small size, the ratio of the contact area with respect to the polycrystalline area increases, making it difficult to increase the operation speed. In order to reduce the contact area of the polycrystalline silicon layer, this invention deals with the structure in which the polycrystalline silicon layer is brought into contact with a portion near the edge of the convex semiconductor layer maintaining a small size and a high precision.
摘要翻译：能够高速运行的双极晶体管。在设计用于高速运行的双极晶体管中，用作基极效应的多晶硅层是相对于缺少精度或倾向于增加的基极区域的接触面积。此外，当晶体管形成为小尺寸时，接触面积相对于多晶面积的比率增加，使得难以提高操作速度。为了减少多晶硅层的接触面积，本发明涉及多晶硅层与凸半导体层的边缘附近的部分接触的结构，保持小尺寸和高精度。

15. 发明授权

US08212615B2 Variable-gain amplifier circuit and wireless communication device integrated circuit equipped therewith 有权
标题翻译：可变增益放大器电路和配备其的无线通信设备集成电路
公开(公告)号：US08212615B2
公开(公告)日：2012-07-03
申请号：US12765010
申请日：2010-04-22
申请人： Toru Masuda , Nobuhiro Shiramizu , Takahiro Nakamura , Katsuyoshi Washio
发明人： Toru Masuda , Nobuhiro Shiramizu , Takahiro Nakamura , Katsuyoshi Washio
IPC分类号： H03F3/45 , H03F3/191
CPC分类号： H03G3/3052
摘要： There is disclosed a variable-gain amplifier circuit that operates on a low voltage, exhibits low distortion, provides a wide range of variation, and is suitable for use in a low-power-consumption wireless communication system. The variable-gain amplifier circuit is configured so that a variable-load circuit, which includes three reactance function elements and provides a wide range of impedance variation, is connected to a conductor circuit whose output terminal generates a positive-phase output current proportional to conductance with respect to an input voltage.
摘要翻译：公开了一种在低电压下操作的可变增益放大器电路，具有低失真，提供宽范围的变化，并且适用于低功耗无线通信系统。可变增益放大器电路被配置为使得包括三个电抗功能元件并提供宽范围的阻抗变化的可变负载电路连接到其输出端产生与电导成比例的正相输出电流的导体电路相对于输入电压。

16. 发明授权

US07098740B2 Radio frequency power amplifier and communication system 失效
标题翻译：射频功率放大器和通信系统
公开(公告)号：US07098740B2
公开(公告)日：2006-08-29
申请号：US10688976
申请日：2003-10-21
申请人： Masao Kondo , Toru Masuda , Katsuyoshi Washio
发明人： Masao Kondo , Toru Masuda , Katsuyoshi Washio
IPC分类号： H03F3/68
CPC分类号： H03F3/211 , H03F1/302 , H03F2200/372 , H03F2203/21178
摘要： There is provided not only a radio frequency power amplifier using an SiGe HBT subject to a little amplification distortion, but also a communication system using the same. A conventional radio frequency power amplifier provides base bias paths of transistors Q1 through QN (SiGe HBT) with bias resistors R11 through R1N having resistance values three to five times higher than those of a ballast resistor attached to each transistor's base. A coil LB is provided in parallel with the bias resistor as a means for compensating a voltage drop due to direct current component IDC flowing through the bias resistor. Addition of the bias resistor suppresses non-linearity of low-frequency variations in an output current. Addition of the coil compensates for voltage drop. Accordingly, the maximum linear output power can be improved. As a result, it is possible to provide the power amplifier subject to a little amplification distortion within a wide output range.
摘要翻译：不仅提供使用SiGe HBT的射频功率放大器，而且具有很小的放大失真，而且还提供了使用它的通信系统。传统的射频功率放大器提供具有偏置电阻器R11至R11的晶体管Q 1至Q N（SiGe HBT）的基极偏置路径， SUB> 1N 的电阻值是连接到每个晶体管基极的镇流电阻的三到五倍。作为用于补偿流过偏置电阻器的直流分量I DC的电压降的装置，设置有与偏压电阻并联的线圈L B B。增加偏置电阻抑制输出电流中低频变化的非线性。线圈的添加补偿电压降。因此，可以提高最大线性输出功率。结果，可以在宽的输出范围内提供具有小的放大失真的功率放大器。

17. 发明申请

US20050001238A1 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050001238A1
公开(公告)日：2005-01-06
申请号：US10855378
申请日：2004-05-28
申请人： Eiji Oue , Katsuyoshi Washio , Hiromi Shimamoto , Katsuya Oda , Makoto Miura
发明人： Eiji Oue , Katsuyoshi Washio , Hiromi Shimamoto , Katsuya Oda , Makoto Miura
IPC分类号： H01L21/331 , H01L29/732 , H01L29/737 , H01L31/0328
CPC分类号： H01L29/66287 , H01L29/7322
摘要： A bipolar transistor is provided in which both the base resistance and the base-collector capacitance are reduced and which is capable of operating at a high cutoff frequency. The semiconductor device is structured so that the emitter and extrinsic base are separated from each other by an insulator sidewall and the bottom faces of the insulator sidewall, and the emitter are approximately on the same plane. The extrinsic base electrode and the collector region are separated from each other by an insulator.
摘要翻译：提供双极晶体管，其中基极电阻和基极集电极电容都减小，并且能够以高截止频率工作。半导体器件被构造成使得发射极和非本征基极通过绝缘体侧壁和绝缘体侧壁的底面彼此分离，并且发射极大致在同一平面上。外部基极和集电极区域通过绝缘体彼此分离。

18. 发明授权

US06667489B2 Heterojunction bipolar transistor and method for production thereof 有权
标题翻译：异质结双极晶体管及其制造方法
公开(公告)号：US06667489B2
公开(公告)日：2003-12-23
申请号：US10299837
申请日：2002-11-20
申请人： Isao Suzumura , Katsuya Oda , Katsuyoshi Washio
发明人： Isao Suzumura , Katsuya Oda , Katsuyoshi Washio
IPC分类号： H01L2906
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A high-speed heterojunction bipolar transistor in a large injection of electrons from the emitter and a method for production thereof. In a typical example of the SiGeC heterojunction bipolar transistor, the collector has a layer of n-type single-crystal Si and a layer of n-type single-crystal SiGe, the base is a layer of heavily doped p-type single-crystal SiGeC, and the emitter is a layer of n-type single-crystal Si. At the heterointerface between the layer of n-type single-crystal SiGe and the layer of p-type single-crystal SiGeC, the bandgap of the p-type single-crystal SiGeC is larger than that of the layer of n-type single-crystal SiGe. Even though the effective neutral base expands due to an increase in electrons injected from the emitter, no energy barrier occurs in the conduction band at the heterointerface between the layer of n-type single-crystal SiGe and the layer of p-type single-crystal SiGeC. Thus, the diffusion of electrons is not inhibited and it is possible to realize high-speed heterojunction bipolar transistors even in the high injection state.
摘要翻译：从发射极大量注入电子的高速异质结双极晶体管及其制造方法。在SiGeC异质结双极晶体管的典型实例中，集电体具有n型单晶Si层和n型单晶SiGe层，基极是重掺杂p型单晶层 SiGeC，发射极是n型单晶Si层。在n型单晶SiGe层和p型单晶SiGeC层之间的异质界面处，p型单晶SiGeC的带隙大于n型单晶SiGeC层的带隙，水晶SiGe。即使有效的中性碱基由于从发射体注入的电子的增加而扩大，在n型单晶SiGe层与p型单晶层之间的异质界面的导带中也不发生能量势垒 SiGeC。因此，电子的扩散不被抑制，即使在高注入状态下也可以实现高速异质结双极晶体管。

19. 发明授权

US06472753B2 BICMOS semiconductor integrated circuit device and fabrication process thereof 失效
公开(公告)号：US06472753B2
公开(公告)日：2002-10-29
申请号：US09811478
申请日：2001-03-20
申请人： Masao Kondo , Katsuyoshi Washio , Eiji Oue , Hiromi Shimamoto
发明人： Masao Kondo , Katsuyoshi Washio , Eiji Oue , Hiromi Shimamoto
IPC分类号： H01L2348
CPC分类号： H01L27/0623 , H01L21/8249 , H01L2924/0002 , H01L2924/00
摘要： Provided is a BiCOMOS semiconductor integrated circuit device which comprises a semiconductor substrate having an insulating layer internally and partially embedded therein and a semiconductor layer deposited on the insulating layer, an insulated gate type transistor formed in the semiconductor layer, a highly-doped collector layer of a bipolar transistor embedded in an insulating-layer-free portion of the semiconductor substrate, and a low-doped collector layer disposed on the highly-doped collector layer of the bipolar transistor, wherein the height level of the lower portion of the low-doped collector layer is below the height level of the lower portion of the insulating layer so as to attain high breakdown voltage and high speed operation of the bipolar transistor.

20. 发明授权

US07095043B2 Semiconductor device, semiconductor circuit module and manufacturing method of the same 失效
标题翻译：半导体器件，半导体电路模块及其制造方法
公开(公告)号：US07095043B2
公开(公告)日：2006-08-22
申请号：US10790190
申请日：2004-03-02
申请人： Katsuya Oda , Nobuyuki Sugii , Makoto Miura , Isao Suzumura , Katsuyoshi Washio
发明人： Katsuya Oda , Nobuyuki Sugii , Makoto Miura , Isao Suzumura , Katsuyoshi Washio
IPC分类号： H01L29/06 , H01L31/0328
CPC分类号： H01L29/66068 , H01L21/823807 , H01L27/0922 , H01L29/1054 , H01L29/1608
摘要： An (SiGe)C layer having a stoichiometric ratio of about 1:1 is locally formed on an Si layer, a large forbidden band width semiconductor device is prepared inside the layered structure thereof and an Si semiconductor integrated circuit is formed in the regions not formed with the layered structure, whereby high frequency high power operation of the device is enabled by the large forbidden band width semiconductor device and high performance is attained by hybridization of the Si integrated circuit.
摘要翻译：在Si层上局部地形成化学计量比为约1:1的An（SiGe）C层，在其层叠结构内制备大的禁带宽半导体器件，并且在未形成的区域中形成Si半导体集成电路具有分层结构，由此通过大的禁带宽半导体器件能够实现器件的高频高功率操作，并且通过Si集成电路的杂交获得高性能。

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