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    • 13. 发明授权
    • Encoding of 8B10B control characters
    • 8B10B控制字符的编码
    • US07061407B1
    • 2006-06-13
    • US11151935
    • 2005-06-14
    • Hyun Soo Lee
    • Hyun Soo Lee
    • H03M7/00
    • H03M7/06
    • An encoder includes a first storage array having a first set of values, a second storage array having a second set of values, and a selection circuit. Each of the first and second storage arrays have address ports coupled to receive a first or second portion of an input value, and are adapted to output a first or second value of the first or second set in response to a value of the first or second portion of the input value, respectively. The selection circuit has input ports coupled to the first storage array, to the second storage array, and for receiving the input value. The selection circuit is adapted to output the second value from the second storage array as an encoded value of the input value or the first value from the first storage array as the encoded value.
    • 编码器包括具有第一组值的第一存储阵列,具有第二组值的第二存储阵列和选择电路。 第一和第二存储阵列中的每一个具有耦合以接收输入值的第一或第二部分的地址端口,并且适于响应于第一或第二存储阵列的值输出第一或第二集合的第一或第二值 输入值的一部分。 选择电路具有耦合到第一存储阵列,第二存储阵列和用于接收输入值的输入端口。 选择电路适于从第二存储阵列输出第二值作为来自第一存储阵列的输入值的编码值或作为编码值的第一值。
    • 18. 发明授权
    • MPEG2 transport decoder
    • MPEG2传输解码器
    • US5841472A
    • 1998-11-24
    • US559634
    • 1995-11-20
    • Chai Yeol RimHyun Soo Lee
    • Chai Yeol RimHyun Soo Lee
    • H04N19/102H04N5/00H04N7/52H04N19/00H04N19/152H04N19/423H04N19/44H04N19/70H04N7/24
    • H04N21/434H04N19/00H04N19/61H04N7/52H04N19/70
    • Disclosed is an MPEG2 transport decoder including a transport parser unit for storing each syntax field value by parsing, outputting each data identified with the packet identifier PID after collecting from each packet data and outputting the interrupt signal if a pointed resister value of the resist values is set; a CPU interface unit for providing an interface between the resister file of said transport parser unit and each decoder and outputting a signal selecting a transport parser unit or a video decoder, an audio decoder, a data decoder and a memory by decoding the address; a CPU for reading the interrupt resister from said CPU interface unit once an interrupt signal is inputted, detecting if the interrupt signal is inputted from said transport parser unit or from the video decoder, the audio decoder and the data decoder, and decoding according to the program on a memory unit; a memory unit for storing a program of the operations of said CPU; and a decoder interface unit for controlling in order to exchanging the data among said CPU, said transport parser unit and said video, audio, data decoders.
    • 公开了一种MPEG2传输解码器,其包括用于通过解析来存储每个语法字段值的传输解析器单元,从每个分组数据收集之后输出由分组标识符PID识别的每个数据,并且如果抗蚀剂值的指向寄存器值为 组; CPU接口单元,用于在所述传输解析器单元的寄存器文件和每个解码器之间提供接口,并通过解码地址来输出选择传输解析器单元或视频解码器,音频解码器,数据解码器和存储器的信号; 一旦中断信号被输入,CPU就从所述CPU接口单元读取中断电阻,检测中断信号是否从所述传输解析器单元或视频解码器,音频解码器和数据解码器输入,以及按照 程序存储单元; 用于存储所述CPU的操作的程序的存储单元; 以及解码器接口单元,用于控制以便在所述CPU,所述传输解析器单元和所述视频,音频数据解码器之间交换数据。