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11. 发明授权

US08374842B2 Device emulation support apparatus, device emulation support method, device emulation support circuit and information processor 失效
标题翻译：设备仿真支持设备，设备仿真支持方法，设备仿真支持电路和信息处理器
公开(公告)号：US08374842B2
公开(公告)日：2013-02-12
申请号：US12670929
申请日：2009-05-20
申请人： Katsushige Amano , Tadao Tanikawa
发明人： Katsushige Amano , Tadao Tanikawa
IPC分类号： G06F9/455
CPC分类号： G06F11/261
摘要： An access monitoring section (11) obtains access information including an address conforming to an address stored in a monitoring address setting section (10) from an access signal output from a CPU (1) to a peripheral device (3). An access judging section (13) compares the access information received from the access monitoring section (11) and the last access information stored in an access storing section (12), and stores the obtained access information in the access storing section (12) and requests the transmission of an exception generation notification to an exception generating section (14) when the received access information is different from the last access information while excluding the last access information stored in the access storing section (12) from access information to be compared when the received access information is the same as the last access information. By this construction, throughput can be reduced at the time of emulation and the peripheral device can be efficiently emulated.
摘要翻译：访问监视部分（11）从从CPU（1）输出到外围设备（3）的访问信号获得包括符合监视地址设置部分（10）中存储的地址的地址的访问信息。访问判断部（13）将从访问监视部（11）接收的访问信息与存储在访问存储部（12）中的最后访问信息进行比较，并将获取的访问信息存储在访问存储部（12）中，当所接收的访问信息与最后访问信息不同时，请求将异常生成通知发送到异常生成部（14），同时从访问存储部（12）中存储的最后访问信息中排除要进行比较的访问信息所接收的访问信息与最后访问信息相同。通过这种结构，可以在仿真时减少吞吐量并且可以有效地模拟外围设备。

12. 发明授权

US08726056B2 Clock control device, clock control method, clock control program and integrated circuit 失效
标题翻译：时钟控制装置，时钟控制方式，时钟控制程序和集成电路
公开(公告)号：US08726056B2
公开(公告)日：2014-05-13
申请号：US13346023
申请日：2012-01-09
申请人： Ryo Yokoyama , Tadao Tanikawa
发明人： Ryo Yokoyama , Tadao Tanikawa
IPC分类号： G06F1/32
CPC分类号： G06F9/3869 , G06F1/3203 , G06F1/3215 , G06F1/3237 , G06F1/324 , G06F1/3275 , G06F9/3824 , G06F9/3836 , Y02D10/126 , Y02D10/128 , Y02D10/14
摘要： An instruction detecting section (235) detects whether or not there is any succeeding instruction executable regardless of an order based on a data dependency relationship between a presently executed instruction and a succeeding instruction following the presently executed instruction. A clock switch judging section (236) receives notification of the start and end of a memory stall, determines whether or not a memory stall is occurring, and judges whether to switch a clock signal to be supplied to a CPU (200) to a low clock signal (239) or to stop the clock signal based on a detection result of the instruction detecting section (235) if it is judged that the memory stall is occurring. A clock switching section (237) switches the clock signal based on judgment by the clock switch judging section (236). By this construction, power consumption can be reduced without reducing performance.
摘要翻译：指令检测部（235）基于当前执行的指令与当前执行的指令之后的后续指令之间的数据依赖关系来检测是否存在任何可执行的后续指令，而不管顺序如何。时钟切换判断部（236）接收存储器停止的开始和结束的通知，判定是否发生存储器停止，并且判断是否将提供给CPU（200）的时钟信号切换为低时钟信号（239），或者如果判断出存储器停止发生，则基于指令检测部分（235）的检测结果停止时钟信号。时钟切换部（237）根据时钟切换判断部（236）的判断来切换时钟信号。通过这种结构，可以降低功耗而不降低性能。

13. 发明申请

US20100231959A1 EXECUTION ORDER DETERMINING DEVICE, EXECUTION ORDER DETERMINING PROGRAM, EXECUTION ORDER DETERMINING CIRCUIT, AND INFORMATION PROCESSING DEVICE 有权
标题翻译：执行订单确定设备，执行订单确定程序，执行订单确定电路和信息处理设备
公开(公告)号：US20100231959A1
公开(公告)日：2010-09-16
申请号：US12675466
申请日：2009-06-25
申请人： Tadao Tanikawa
发明人： Tadao Tanikawa
IPC分类号： G06F3/12
CPC分类号： G06F9/4881
摘要： A job control information storing section (111) stores execution conditions under which execution of the respective tasks is started, and an execution order of the tasks. A job executing section (101) executes the tasks in accordance with the execution order. A job execution administering section (102) monitors a state of the task being executed to detect the task whose state is shifted to a process standby state of waiting for a response from another one of the tasks, based on the execution conditions, and responds to a request of executing the another task from the task whose state is shifted to the process standby state, in response to accepting the request from the task whose state is shifted to the process standby state. A virtual task generating section (121) generates a virtual task as a copy of the task whose state is detected to be shifted to the process standby state. A virtual task registering section (122) adds the virtual task to the execution order stored in the task control information storing section (111) to concurrently execute the virtual task with the task whose state is shifted to the process standby state. This enables to efficiently carry out scheduling of the tasks.
摘要翻译：作业控制信息存储部（111）存储开始执行各个任务的执行条件和任务的执行顺序。作业执行部（101）根据执行顺序执行任务。作业执行管理部（102）基于执行条件来监视被执行的任务的状态，以检测其状态被转移到等待来自另一个任务的响应的进程待机状态的任务，并响应于响应于接受来自其状态转移到进程待机状态的任务的请求，从其状态转移到进程待机状态的任务执行另一任务的请求。虚拟任务生成部（121）生成虚拟任务作为其状态被检测为移动到处理待机状态的任务的副本。虚拟任务登记部（122）将虚拟任务与存储在任务控制信息存储部（111）中的执行顺序相加，并将其状态转移到处理待机状态的任务并行执行。这使得能够有效地执行任务的调度。

14. 发明授权

US08544011B2 Generation and concurrent execution of a virtual task in an execution order determining system 有权
标题翻译：执行顺序确定系统中的虚拟任务的生成和并发执行
公开(公告)号：US08544011B2
公开(公告)日：2013-09-24
申请号：US12675466
申请日：2009-06-25
申请人： Tadao Tanikawa
发明人： Tadao Tanikawa
IPC分类号： G06F9/46
CPC分类号： G06F9/4881
摘要： A job control information storing section stores execution conditions under which execution of tasks is started, and an execution order of the tasks. A job executing section executes the tasks. A job execution administering section monitors a state of the task being executed to detect the task whose state is shifted to a process standby state of waiting for a response from another one of the tasks, based on the execution conditions, and responds to a request of executing the another task from the task whose state is shifted, in response to accepting the request from the task whose state is shifted. A virtual task generating section generates a virtual task as a copy of the task whose state is detected to be shifted. A virtual task registering section adds the virtual task to the execution order to concurrently execute the virtual task with the task whose state is shifted.
摘要翻译：作业控制信息存储部存储开始执行任务的执行条件和任务的执行顺序。作业执行部分执行任务。作业执行管理部分基于执行条件来监视被执行的任务的状态，以检测其状态被转移到等待来自另一个任务的响应的进程备用状态的任务，并响应于响应于接受来自状态移动的任务的请求，从状态被移动的任务执行另一任务。虚拟任务生成部分生成虚拟任务作为检测状态被移动的任务的副本。虚拟任务注册部分将虚拟任务添加到执行顺序，以同时执行其状态被移动的任务的虚拟任务。

15. 发明授权

US08117474B2 CPU clock control during cache memory stall 有权
标题翻译：缓存内存停止时CPU时钟控制
公开(公告)号：US08117474B2
公开(公告)日：2012-02-14
申请号：US12526365
申请日：2008-12-10
申请人： Ryo Yokoyama , Tadao Tanikawa
发明人： Ryo Yokoyama , Tadao Tanikawa
IPC分类号： G06F1/32
CPC分类号： G06F9/3869 , G06F1/3203 , G06F1/3215 , G06F1/3237 , G06F1/324 , G06F1/3275 , G06F9/3824 , G06F9/3836 , Y02D10/126 , Y02D10/128 , Y02D10/14
摘要： An instruction detecting section (235) detects whether or not there is any succeeding instruction executable regardless of an order based on a data dependency relationship between a presently executed instruction and a succeeding instruction following the presently executed instruction. A clock switch judging section (236) receives notification of the start and end of a memory stall, determines whether or not a memory stall is occurring, and judges whether to switch a clock signal to be supplied to a CPU (200) to a low clock signal (239) or to stop the clock signal based on a detection result of the instruction detecting section (235) if it is judged that the memory stall is occurring. A clock switching section (237) switches the clock signal based on judgment by the clock switch judging section (236). By this construction, power consumption can be reduced without reducing performance.
摘要翻译：指令检测部（235）基于当前执行的指令与当前执行的指令之后的后续指令之间的数据依赖关系来检测是否存在任何可执行的后续指令，而不管顺序如何。时钟切换判断部（236）接收存储器停止的开始和结束的通知，判定是否发生存储器停止，并且判断是否将提供给CPU（200）的时钟信号切换为低时钟信号（239），或者如果判断出存储器停止发生，则基于指令检测部分（235）的检测结果停止时钟信号。时钟切换部（237）根据时钟切换判断部（236）的判断来切换时钟信号。通过这种结构，可以降低功耗而不降低性能。

16. 发明申请

US20120331465A1 VIRTUAL MACHINE SYSTEM, VIRTUAL MACHINE CONTROL METHOD, VIRTUAL MACHINE CONTROL APPLICATION, AND SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：虚拟机系统，虚拟机控制方法，虚拟机控制应用和半导体集成电路
公开(公告)号：US20120331465A1
公开(公告)日：2012-12-27
申请号：US13583151
申请日：2011-09-12
申请人： Tadao Tanikawa
发明人： Tadao Tanikawa
IPC分类号： G06F9/455
CPC分类号： G06F9/5077 , G06F12/1491 , G06F21/53 , G06F2212/151
摘要： A memory protection unit controls access by virtual machines to memory areas. By having a hypervisor executed by a processor and the memory protection unit cooperate, access to memory areas by each virtual machine is controlled such that access to designated areas is forbidden. Accordingly, each virtual machine is unable to access programs, data, and so on stored in areas forbidden thereto.
摘要翻译：内存保护单元控制虚拟机访问内存区域。通过使处理器执行的管理程序和存储器保护单元协作，控制每个虚拟机对存储器区域的访问，使得禁止对指定区域的访问。因此，每个虚拟机不能访问存储在被禁止的区域中的程序，数据等。

17. 发明申请

US20100325469A1 CLOCK CONTROL DEVICE, CLOCK CONTROL METHOD, CLOCK CONTROL PROGRAM AND INTEGRATED CIRCUIT 有权
标题翻译：时钟控制设备，时钟控制方法，时钟控制程序和集成电路
公开(公告)号：US20100325469A1
公开(公告)日：2010-12-23
申请号：US12526365
申请日：2008-12-10
申请人： Ryo Yokoyama , Tadao Tanikawa
发明人： Ryo Yokoyama , Tadao Tanikawa
IPC分类号： G06F9/30 , G06F1/04
CPC分类号： G06F9/3869 , G06F1/3203 , G06F1/3215 , G06F1/3237 , G06F1/324 , G06F1/3275 , G06F9/3824 , G06F9/3836 , Y02D10/126 , Y02D10/128 , Y02D10/14
摘要： An instruction detecting section (235) detects whether or not there is any succeeding instruction executable regardless of an order based on a data dependency relationship between a presently executed instruction and a succeeding instruction following the presently executed instruction. A clock switch judging section (236) receives notification of the start and end of a memory stall, determines whether or not a memory stall is occurring, and judges whether to switch a clock signal to be supplied to a CPU (200) to a low clock signal (239) or to stop the clock signal based on a detection result of the instruction detecting section (235) if it is judged that the memory stall is occurring. A clock switching section (237) switches the clock signal based on judgment by the clock switch judging section (236). By this construction, power consumption can be reduced without reducing performance.
摘要翻译：指令检测部（235）基于当前执行的指令与当前执行的指令之后的后续指令之间的数据依赖关系来检测是否存在任何可执行的后续指令，而不管顺序如何。时钟切换判断部（236）接收存储器停止的开始和结束的通知，判定是否发生存储器停止，并且判断是否将提供给CPU（200）的时钟信号切换为低时钟信号（239），或者如果判断出存储器停止发生，则基于指令检测部分（235）的检测结果停止时钟信号。时钟切换部（237）根据时钟切换判断部（236）的判断来切换时钟信号。通过这种结构，可以降低功耗而不降低性能。

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