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11. 发明授权

US09818752B2 Memory metal scheme 有权
公开(公告)号：US09818752B2
公开(公告)日：2017-11-14
申请号：US15153872
申请日：2016-05-13
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Derek C. Tao , Jacklyn Chang , Kuoyuan (Peter) Hsu , Yukit Tang
IPC分类号： G11C5/02 , G11C5/06 , H01L27/11 , H01L23/50 , G11C11/418 , G11C11/419 , H01L23/522 , H01L23/528 , H01L27/02 , H01L27/06
CPC分类号： H01L27/11 , G11C5/02 , G11C5/06 , G11C11/418 , G11C11/419 , G11C2213/71 , H01L23/50 , H01L23/5226 , H01L23/528 , H01L27/0207 , H01L27/0688 , H01L27/1116 , H01L2224/73265
摘要： A method of fabricating a memory includes forming a first portion of a first line in a first metal layer, forming a first portion of a second line in the first metal layer, forming a second portion of the first line in a second metal layer, and forming a second portion of the second line in a third metal layer. The first line is over a plurality of memory cells. The second line is over the plurality of memory cells, the first line is electrically isolated from the second line, and the first line and the second line extend in a same direction. The second metal layer is over the first metal layer. The third metal layer is over the second metal layer and the third metal layer is electrically isolated from the first line.

12. 发明授权

US09812177B2 Circuit, method of using the circuit and memory macro including the circuit 有权
公开(公告)号：US09812177B2
公开(公告)日：2017-11-07
申请号：US14823107
申请日：2015-08-11
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Bing Wang , Kuoyuan (Peter) Hsu
IPC分类号： G11C5/06 , G11C7/10 , G11C7/18 , G11C8/08 , G11C8/12 , G11C8/16 , G11C11/418
CPC分类号： G11C5/063 , G11C7/1012 , G11C7/106 , G11C7/18 , G11C8/08 , G11C8/12 , G11C8/16 , G11C11/418
摘要： A circuit includes a first latch for generating a first latched signal; and a first comparator for comparing the first latched signal and a write address, and generating a first comparator signal. The circuit includes a first logic circuit for receiving the first comparator signal and a fourth latched signal, and generating a first logic circuit output signal; and a second latch for receiving the first logic circuit output signal and generating a second latched signal. The circuit includes a third latch for generating a third latched signal; and a second comparator for comparing the third latched signal and a read address, and generating a second comparator signal. The circuit includes a second logic circuit for receiving the second comparator signal and the second latched signal, and generating a second logic circuit signal; and a fourth latch for receiving the second logic circuit signal and generating the fourth latched signal.

13. 发明授权

US09378806B2 Boosting voltage level 有权
标题翻译：提升电压电平
公开(公告)号：US09378806B2
公开(公告)日：2016-06-28
申请号：US14107017
申请日：2013-12-16
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Bing Wang , Kuoyuan (Peter) Hsu , Annie-Li-Keow Lum
IPC分类号： G11C11/00 , G11C11/419 , G11C7/12
CPC分类号： G11C11/419 , G11C7/12
摘要： A circuit comprises a driver, a first capacitive device, and a second capacitive device. The driver has an input node, an output node, and a driver supply voltage node. The first capacitive device has a first terminal and a second terminal. The second capacitive device has a first terminal and a second terminal. The first terminal of the first capacitive device is configured to receive a first signal. The second terminal of the first capacitive device is coupled with the driver supply voltage node. The output of the driver is coupled with a first end of the second capacitive device.
摘要翻译：电路包括驱动器，第一电容器件和第二电容器件。驱动器具有输入节点，输出节点和驱动器电源电压节点。第一电容性装置具有第一端子和第二端子。第二电容性装置具有第一端子和第二端子。第一电容性装置的第一端被配置为接收第一信号。第一电容性装置的第二端子与驱动器电源电压节点耦合。驱动器的输出与第二电容性装置的第一端耦合。

14. 发明授权

US09245594B2 Switching circuit 有权
标题翻译：开关电路
公开(公告)号：US09245594B2
公开(公告)日：2016-01-26
申请号：US14597897
申请日：2015-01-15
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Bing Wang , Kuoyuan (Peter) Hsu
IPC分类号： G11C7/00 , G11C5/14 , G11C5/02
CPC分类号： H03K17/04 , G11C5/025 , G11C5/14 , G11C5/148 , G11C16/30 , H03K17/063 , H03K17/284 , H03K17/6872 , H03K17/6877
摘要： A first transistor is turned on based on a first control signal provided to a first terminal of the first transistor. A second control signal is generated by a logic device based on a first input signal and a second input signal. The first input signal is controlled by a logical value stored by a keeper circuit and based on the first control signal, and the second input signal is generated by inverting the first control signal. A second transistor is turned on based on the second control signal provided to a first terminal of the second transistor. A second terminal of the first transistor is coupled with a second terminal of the second transistor.
摘要翻译：第一晶体管基于提供给第一晶体管的第一端的第一控制信号而导通。第二控制信号由逻辑器件基于第一输入信号和第二输入信号产生。第一输入信号由保持器电路存储的逻辑值并基于第一控制信号控制，第二输入信号通过反相第一控制信号产生。基于提供给第二晶体管的第一端子的第二控制信号，第二晶体管导通。第一晶体管的第二端与第二晶体管的第二端耦合。

15. 发明授权

US09099201B2 Multiple bitcells tracking scheme semiconductor memory array 有权
标题翻译：多位单元跟踪方案半导体存储器阵列
公开(公告)号：US09099201B2
公开(公告)日：2015-08-04
申请号：US14279424
申请日：2014-05-16
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Derek C. Tao , Bing Wang , Kuoyuan (Peter) Hsu , Jacklyn Victoria Chang , Young Suk Kim
IPC分类号： G11C5/06 , G11C11/419 , G11C7/08 , G11C7/22 , G11C5/02 , G11C7/18
CPC分类号： G11C11/419 , G11C5/025 , G11C5/063 , G11C7/08 , G11C7/18 , G11C7/227
摘要： A memory array includes a memory segment having at least one memory bank. The at least one memory bank includes an array of memory cells, and wherein at least two first read tracking cells are disposed in a read tracking column of the at least one memory bank. The memory array further includes a read tracking circuit coupled to the at least two first read tracking cells. Outputs of the at least two first read tracking cells are connected to a tracking bit connection line (TBCL). A tracking circuit connected to the TBCL is configured to output a tracking-cells output signal to generate a global tracking result signal to a memory control circuitry. The memory control circuitry is configured to reset a memory clock based on the global tracking result signal.
摘要翻译：存储器阵列包括具有至少一个存储体的存储器段。所述至少一个存储体包括存储器单元的阵列，并且其中至少两个第一读取跟踪单元被布置在所述至少一个存储体的读取跟踪列中。存储器阵列还包括耦合到至少两个第一读取跟踪单元的读取跟踪电路。至少两个第一读取跟踪单元的输出连接到跟踪位连接线（TBCL）。连接到TBCL的跟踪电路被配置为输出跟踪单元输出信号以产生到存储器控制电路的全局跟踪结果信号。存储器控制电路被配置为基于全局跟踪结果信号复位存储器时钟。

16. 发明授权

US09053818B2 Mode changing circuitry 有权
标题翻译：模式改变电路
公开(公告)号：US09053818B2
公开(公告)日：2015-06-09
申请号：US14549043
申请日：2014-11-20
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Bing Wang , Kuoyuan (Peter) Hsu
IPC分类号： G11C7/00 , G11C11/417
CPC分类号： G11C11/417 , G11C2207/2227
摘要： A circuit includes a PMOS transistor, an NMOS transistor, and a logic level generation section comprising an input and a logic level output. The PMOS gate receives an input voltage having a voltage level determined based on an operational voltage, the PMOS drain is coupled to the NMOS drain and the input of the logic level generation section, and the PMOS source is coupled to the operational voltage. The NMOS gate receives a voltage that causes the NMOS transistor to have a first driving capability. The first driving capability of the NMOS transistor is less than that of the PMOS transistor if the input voltage has a voltage level greater than a predetermined voltage level.
摘要翻译：电路包括PMOS晶体管，NMOS晶体管和包括输入和逻辑电平输出的逻辑电平产生部分。 PMOS栅极接收具有基于工作电压确定的电压电平的输入电压，PMOS漏极耦合到NMOS漏极和逻辑电平产生部分的输入，PMOS源耦合到工作电压。 NMOS栅极接收使NMOS晶体管具有第一驱动能力的电压。如果输入电压具有大于预定电压电平的电压电平，则NMOS晶体管的第一驱动能力小于PMOS晶体管的驱动能力。

17. 发明授权

US08817568B2 Dual rail memory 有权
标题翻译：双轨内存
公开(公告)号：US08817568B2
公开(公告)日：2014-08-26
申请号：US13646238
申请日：2012-10-05
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Derek C. Tao , Kuoyuan (Peter) Hsu , Dong Sik Jeong , Young Suk Kim , Young Seog Kim , Yukit Tang
IPC分类号： G11C5/14
CPC分类号： G11C5/14
摘要： A memory array comprises a plurality of memory cells arranged in a plurality of rows and a plurality of columns. A column of the plurality of columns includes a first voltage circuit coupled to internal first nodes of memory cells in the one of the plurality of columns and a second voltage circuit coupled to internal second nodes of the memory cells in the one of the plurality of columns. The first voltage circuit is configured to provide one of a first supply voltage and a second supply voltage lower than the first supply voltage to the internal first nodes. The second voltage circuit is configured to provide one of a first reference voltage and a second reference voltage higher than the first reference voltage to the internal second nodes.
摘要翻译：存储器阵列包括以多行和多列布置的多个存储单元。多列的列包括耦合到多列中的一列的存储器单元的内部第一节点的第一电压电路和耦合到多列中的一列的存储单元的内部第二节点的第二电压电路。第一电压电路被配置为向内部第一节点提供低于第一电源电压的第一电源电压和第二电源电压中的一个。第二电压电路被配置为向内部第二节点提供高于第一参考电压的第一参考电压和第二参考电压之一。

18. 发明授权

US11443786B2 Memory circuit including tracking circuit 有权
公开(公告)号：US11443786B2
公开(公告)日：2022-09-13
申请号：US17326869
申请日：2021-05-21
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Kuoyuan (Peter) Hsu , Jacklyn Chang
IPC分类号： G11C7/22 , G11C7/14 , G11C7/12 , G11C29/50 , G11C11/404 , G11C11/4094
摘要： A memory circuit includes: memory cells each including a storage transistor corresponding to a predetermined configuration; and a tracking circuit configured to elapse a variable waiting period during which a voltage on a first node decreases from a first level to a second level, the tracking circuit including a first finger circuit coupled between a first node of a tracking bit line and a reference voltage node, the first finger circuit including a first set of first tracking cells, each first tracking cell including a first shadow transistor corresponding to the predetermined configuration, gate terminals of the first shadow transistors being coupled with a tracking word line; and a second finger circuit coupled between the first node and the reference voltage node; and a first switch configured to adjust the variable waiting period by selectively coupling the second finger circuit in parallel with the first finger circuit.

19. 发明授权

US11024621B2 Memory circuit layout method 有权
公开(公告)号：US11024621B2
公开(公告)日：2021-06-01
申请号：US16688696
申请日：2019-11-19
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Jacklyn Chang , Kuoyuan (Peter) Hsu
IPC分类号： H01L27/02 , H01L27/112 , H01L23/528 , H01L23/522 , G06F30/392
摘要： A method includes placing first and second oxide diffusion (OD) layout patterns in a layout design corresponding to first, second, third, and fourth memory cells of a memory circuit. The first OD layout pattern extends along a first direction and has a first source portion shared between the first and second memory cells, and the second OD layout pattern extends along the first direction and has a second source portion shared between the third and fourth memory cells. The method includes placing a first conductive layout pattern in the layout diagram, the first conductive layout pattern corresponding to a first conductive structure under a lowest via plug layer of the memory circuit, extending along a second direction, and overlapping the first source portion and the second source portion. The method is wholly or partially performed by using a hardware processor.

20. 发明授权

US10490544B2 Memory circuit layout 有权
公开(公告)号：US10490544B2
公开(公告)日：2019-11-26
申请号：US15863090
申请日：2018-01-05
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Jacklyn Chang , Kuoyuan (Peter) Hsu
IPC分类号： H01L27/02 , H01L27/112 , H01L23/528 , H01L23/522 , G06F17/50
CPC分类号： H01L27/0207 , G06F17/5072 , H01L23/528 , H01L23/5226 , H01L27/11226
摘要： A memory circuit layout design includes first, second, third, and fourth memory cell regions abutting one another and corresponding to respective first, second, third, and fourth memory cells of the memory circuit. A first oxide diffusion (OD) layout pattern corresponds to a first active structure for forming the first and second memory cells, extends along a first direction, and has a shared source portion overlapping the first and second memory cell regions. A second OD layout pattern corresponds to a second active structure for forming the third and fourth memory cells, extends along the first direction, and has a shared source portion overlapping the third and fourth memory cell regions. A first conductive layout pattern corresponds to a first conductive structure under a lowest via plug layer of the memory circuit, extends along a second direction, and overlaps the shared source portions of the first and second OD layout patterns.

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