专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US07141378B2 Exploring fluorophore microenvironments 有权
标题翻译：探索荧光团微环境
公开(公告)号：US07141378B2
公开(公告)日：2006-11-28
申请号：US11173814
申请日：2005-07-01
申请人： Steven C. Miller , Paul B. Comita , Evan F. Cromwell , Christopher B. Shumate
发明人： Steven C. Miller , Paul B. Comita , Evan F. Cromwell , Christopher B. Shumate
IPC分类号： C12Q1/68 , G01N33/53
CPC分类号： G01N33/582 , B82Y5/00 , B82Y10/00 , C12Q1/6816 , G01N21/6408 , G01N21/6428 , G01N21/6445 , G01N2021/6419 , G01N2021/6421 , G01N2021/6432 , G01N2021/6441 , G01N2021/6478 , G01N2021/6484 , G01N2201/067 , G01N2201/0697 , G01N2201/0833 , C12Q2563/107 , C12Q2561/119
摘要： Methods, apparatus, and system, implementing and using techniques for detecting a presence of one or more target analytes in particular regions of interest of one or more samples. One or more samples including objects and one or more target analytes are provided. Some of the target analytes are labeled with a fluorophore and are bound to some of the objects in the samples. The samples are illuminated with fluorescence inducing light and fluorescent light is collected from one or more regions of the one or more samples. At least one anisotropy measurement of the samples is performed to identify regions of interest where one or more target analytes are bound to the objects. The collected fluorescent light from the regions of interest is analyzed to determine a presence of target analytes that are bound to the objects in the one or more samples.
摘要翻译：方法，装置和系统，实施和使用用于检测一个或多个样品的特定感兴趣区域中一种或多种目标分析物的存在的技术。提供了一个或多个样品，包括物体和一种或多种目标分析物。一些目标分析物用荧光团标记，并且与样品中的某些对象结合。用荧光诱导光照射样品，并从一个或多个样品的一个或多个区域采集荧光。进行样品的至少一个各向异性测量以识别一个或多个目标分析物与物体结合的感兴趣区域。分析来自感兴趣区域的收集的荧光以确定与一个或多个样品中的物体结合的目标分析物的存在。

12. 发明授权

US06795900B1 Method and system for storing data at input/output (I/O) interfaces for a multiprocessor system 有权
标题翻译：用于在多处理器系统的输入/输出（I / O）接口处存储数据的方法和系统
公开(公告)号：US06795900B1
公开(公告)日：2004-09-21
申请号：US09910363
申请日：2001-07-20
申请人： Steven C. Miller , Jeffrey S. Kuskin , William A. Huffman , Gregory M. Thorson
发明人： Steven C. Miller , Jeffrey S. Kuskin , William A. Huffman , Gregory M. Thorson
IPC分类号： G06F1200
CPC分类号： G06F12/0817 , G06F2212/2542 , G06F2212/621
摘要： A multiprocessor system and method includes a processing sub-system including a plurality of processors in a processor memory system. A network is operable to couple the processing sub-system to an input/output (I/O) sub-system. The I/O sub-system includes a plurality of I/O interfaces each operable to couple a peripheral device to the multiprocessor system. The I/O interfaces each include a local memory operable to store exclusive read-only copies of data from the processor memory system for use by a corresponding peripheral device.
摘要翻译：多处理器系统和方法包括在处理器存储器系统中包括多个处理器的处理子系统。网络可操作以将处理子系统耦合到输入/输出（I / O）子系统。 I / O子系统包括多个I / O接口，每个I / O接口可操作以将外围设备耦合到多处理器系统。 I / O接口各自包括本地存储器，其可操作以存储来自处理器存储器系统的数据的专用只读副本以供对应的外围设备使用。

13. 发明授权

US06443897B1 Refraction delay error correction using agile beamformer 有权
$Refraction delay error correction using agile beamformer$
标题翻译：使用敏捷波束形成器的折射延迟误差校正
公开(公告)号：US06443897B1
公开(公告)日：2002-09-03
申请号：US09750869
申请日：2000-12-28
申请人： David T. Dubberstein , Steven C. Miller
发明人： David T. Dubberstein , Steven C. Miller
IPC分类号： A61B0800
CPC分类号： G10K11/346
摘要： A method and an apparatus for correcting refraction delay errors on curved probes for all ranges using cordic rotation. The angle &phgr; from the normal of an element to the focus is determined as a function of the angle of cordic rotation. Then a delay error correction is indexed using this angle &phgr;. The angular correction method is efficient in that it uses the inherent property of cordic rotation to calculate the only range-dependent variable required for the correction. Thus the additional hardware required to calculate the corrections is minimal, as the remaining correction variables are vector and range independent.
摘要翻译：一种用于校正所有范围的弯曲探针上的折射延迟误差的方法和装置，其使用线性旋转。从元件的法线到焦点的角度phi被确定为帘线旋转角度的函数。然后使用该角度phi对延迟误差校正进行索引。角度校正方法是有效的，因为它使用线性旋转的固有属性来计算校正所需的唯一的范围因变量。因此，计算校正所需的附加硬件是最小的，因为剩余的校正变量是向量和范围无关的。

14. 发明授权

US06282195B1 Packetized data transmissions in a switched router architecture 失效
标题翻译：交换式路由器架构中的分组化数据传输
公开(公告)号：US06282195B1
公开(公告)日：2001-08-28
申请号：US08780785
申请日：1997-01-09
申请人： Steven C. Miller , James E. Tornes
发明人： Steven C. Miller , James E. Tornes
IPC分类号： H04L1256
CPC分类号： H04L49/253 , H04L49/30
摘要： A switched router for transmitting packetized data concurrently between a plurality of devices coupled to the switched router. The devices are coupled to the I/O ports of the switched router. The switched router is then programmed to route packets of data from various source ports to several destination ports. Different packets may be transmitted concurrently through the switched router. The packets are comprised of a command word containing information corresponding to packet routing, data format, size, and transaction identification. Furthermore, the command word may include a destination identification number for routing the packet to a destination device, a source identification number used by a destination device to send back responses, a transaction number to tag requests that require a response, and a packet type value indicating a particular type of packet. In addition, there may be bits within a packet used to indicate a coherent transaction, guarantee bandwidth, an error during transmission, or a sync barrier for write ordering. Other types of packets may include a fetch and operation packet with increment by one, a fetch and operation packet with decrement by one, a fetch and operation packet with clear, a store and operation packet with increment by one, a store and operation packet with decrement by one, a store and operation packet with a logical OR, and a store and operation packet with a logical AND.
摘要翻译：一种用于在耦合到所述交换路由器的多个设备之间并发地发送分组化数据的交换路由器。这些设备耦合到交换路由器的I / O端口。然后将交换路由器编程为将数据包从各种源端口路由到多个目的端口。可以通过交换路由器同时发送不同的分组。分组由包含对应于分组路由，数据格式，大小和事务标识的信息的命令字组成。此外，命令字可以包括用于将分组路由到目的地设备的目的地标识号，目的地设备用于发送回应用的源标识号，用于标记需要响应的请求的事务号，以及分组类型值指示特定类型的数据包。此外，在用于指示相干事务，保证带宽，传输期间的错误或用于写入顺序的同步屏障中的分组中可能存在位。其他类型的分组可以包括递增1的获取和操作分组，递减1的获取和操作分组，具有清除的获取和操作分组，具有递增1的存储和操作分组，具有递增1的存储和操作分组，递减1，具有逻辑OR的存储和操作分组以及具有逻辑AND的存储和操作分组。

15. 发明授权

US5961461A Method and apparatus for adaptive B-mode image enhancement 失效
标题翻译：用于自适应B模式图像增强的方法和装置
公开(公告)号：US5961461A
公开(公告)日：1999-10-05
申请号：US966376
申请日：1997-11-07
申请人： Larry Y. L. Mo , Steven C. Miller
发明人： Larry Y. L. Mo , Steven C. Miller
IPC分类号： A61B8/00 , G06T1/00 , G06T5/20
CPC分类号： G06T5/20
摘要： A method and an apparatus for adaptively enhancing the B-mode image during post-detection image processing in an ultrasound imaging system. A low pass filter which smooths out speckle and a high pass filter which enhances edges are placed in parallel signal paths connected to the output of an envelope detector in a B-mode processor. The signals in the high pass filter path are logarithmically compressed before high pass filtering. The signals in the low pass filter path are logarithmically compressed after low pass filtering. Respective weighting factors are applied to the low- and high-pass-filtered signals by an adaptive weighting device, which may take the form of a processor or a look-up table. The weighted low- and high-pass-filtered signals are then summed and optionally input to an anti-aliasing low pass filter before decimation and scan conversion.
摘要翻译：一种用于在超声成像系统中的后检测图像处理期间自适应地增强B模式图像的方法和装置。平滑斑点的低通滤波器和增强边缘的高通滤波器被放置在与B模式处理器中的包络检测器的输出端连接的并行信号路径中。在高通滤波之前，高通滤波器路径中的信号是对数压缩的。低通滤波器中的信号在低通滤波后对数压缩。通过自适应加权装置将相应的加权因子应用于低通滤波信号和高通滤波信号，该自适应加权装置可以采取处理器或查找表的形式。然后将加权的低通滤波和高通滤波信号相加，并可选地在抽取和扫描转换之前输入到抗混叠低通滤波器。

16. 发明授权

US5915104A High bandwidth PCI to packet switched router bridge having minimized memory latency 失效
标题翻译：高带宽PCI到分组交换路由器桥，具有最小的内存延迟
公开(公告)号：US5915104A
公开(公告)日：1999-06-22
申请号：US780781
申请日：1997-01-09
申请人： Steven C. Miller
发明人： Steven C. Miller
IPC分类号： G06F13/40 , G06F13/42
CPC分类号： G06F13/4022
摘要： In a computer system, a mechanism for minimizing memory latencies. An improved, high-speed packet switched router is used to route packets quickly and efficiently between the microprocessor and the main memory. The computer system also supports PCI devices by implementing a bridge which acts as an interface between the PCI bus and the packet switched router. In order to minimize the memory latencies for PCI based memory accesses through the bridge, a plurality of read and write buffers are implemented. Write gathering is used to gather a plurality of write transactions on the PCI bus into the write buffers and sent by the bridge as one cache line sized transfer to the routing mechanism. For PCI based read operations, data is pre-fetched from the main memory and stored in the read buffers. Thereby, PCI devices can access the read buffers multiple times to retrieve the requested data.
摘要翻译：在计算机系统中，用于最小化内存延迟的机制。改进的高速分组交换路由器用于在微处理器和主存储器之间快速高效地路由分组。计算机系统还通过实现作为PCI总线和分组交换路由器之间的接口的桥来支持PCI设备。为了最小化通过桥接器的基于PCI的存储器访问的存储器延迟，实现了多个读取和写入缓冲器。写集合用于将PCI总线上的多个写事务收集到写缓冲区中，并由桥作为一个高速缓存线大小传送到路由机制。对于基于PCI的读取操作，数据从主存储器中预取并存储在读缓冲器中。因此，PCI设备可以多次访问读取缓冲区以检索所请求的数据。

17. 发明申请

US20140112872A1 MAGNETIC RELAXOMETRY USING MAGNETIZATION AND MEASUREMENT FIELDS 审中-公开
标题翻译：使用磁化和测量场的磁性离散度
公开(公告)号：US20140112872A1
公开(公告)日：2014-04-24
申请号：US14058050
申请日：2013-10-18
申请人： Edward R Flynn , Victor Gerald Grafe , Steven C. Miller
发明人： Edward R Flynn , Victor Gerald Grafe , Steven C. Miller
IPC分类号： A61K49/16 , G01N33/574
CPC分类号： A61K49/16 , A61K49/1818 , A61K49/1821 , G01N33/574 , G01N33/57449 , G01N33/57492
摘要： The present invention provides methods and apparatuses for detecting, measuring, or locating cells or substances present in even very low concentrations in vivo in subjects, using targeted magnetic nanoparticles and special magnetic systems. The magnetic systems can comprise magnetizing subsystems and sensors subsystems, including as examples SQUID sensors and atomic magnetometers. The magnetic systems can detect, measure, or location particles bound by antibodies to cells or substances of predetermined types. Example magnetic systems are capable of detecting sub-nanogram amounts of these nanoparticles.
摘要翻译：本发明提供了用于使用靶磁性纳米颗粒和特殊磁系统来检测，测量或定位体内甚至非常低的体内浓度的细胞或物质的方法和装置。磁性系统可以包括磁化子系统和传感器子系统，包括例如SQUID传感器和原子磁强计。磁性系统可以检测，测量或定位由细胞或预定类型的物质的抗体结合的颗粒。示例磁系统能够检测亚纳米量的这些纳米颗粒。

18. 发明申请

US20130080709A1 System and Method for Performing Memory Operations In A Computing System 审中-公开
标题翻译：在计算系统中执行存储器操作的系统和方法
公开(公告)号：US20130080709A1
公开(公告)日：2013-03-28
申请号：US13683367
申请日：2012-11-21
申请人： Steven C. Miller , Martin M. Deneroff , Curt F. Schimmel , Larry Rudolph , Charles E. Leiserson , Bradley C. Kuszmaul , Krste Asanovic
发明人： Steven C. Miller , Martin M. Deneroff , Curt F. Schimmel , Larry Rudolph , Charles E. Leiserson , Bradley C. Kuszmaul , Krste Asanovic
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F9/3004 , G06F9/30087 , G06F12/0831
摘要： A processor may operate in one of a plurality of operating states. In a Normal operating state, the processor is not involved with a memory transaction. Upon receipt of a transaction instruction to access a memory location, the processor transitions to a Transaction operating state. In the Transaction operating state, the processor performs changes to a cache line and data associated with the memory location. While in the Transaction operating state, any changes to the data and the cache line are not visible to other processors in the computing system. These changes become visible upon the processor entering a Commit operating state in response to receipt of a commit instruction. After changes become visible, the processor returns to the Normal operating state. If an abort event occurs prior to receipt of the commit instruction, the processor transitions to an Abort operating state where any changes to the data and cache line are discarded.
摘要翻译：处理器可以以多个操作状态中的一个操作。在正常操作状态下，处理器不涉及存储器事务。在接收到访问存储器位置的事务指令时，处理器转换到事务操作状态。在事务操作状态下，处理器执行对高速缓存行的更改和与存储器位置相关联的数据。在事务操作状态下，数据和高速缓存行的任何更改对于计算系统中的其他处理器都不可见。响应于接收到提交指令，处理器进入提交操作状态时，这些更改变得可见。更改变为可见后，处理器返回到正常运行状态。如果在接收提交指令之前发生中止事件，则处理器转换到中止操作状态，其中对数据和高速缓存行的任何改变被丢弃。

19. 发明授权

US08321634B2 System and method for performing memory operations in a computing system 有权
标题翻译：用于在计算系统中执行存储器操作的系统和方法
公开(公告)号：US08321634B2
公开(公告)日：2012-11-27
申请号：US13084280
申请日：2011-04-11
申请人： Steven C. Miller , Martin M. Deneroff , Curt F. Schimmel , Larry Rudolph , Charles E. Leiserson , Bradley C. Kuszmaul , Krste Asanovic
发明人： Steven C. Miller , Martin M. Deneroff , Curt F. Schimmel , Larry Rudolph , Charles E. Leiserson , Bradley C. Kuszmaul , Krste Asanovic
IPC分类号： G06F12/00
CPC分类号： G06F12/0815 , G06F9/3004 , G06F9/30087 , G06F12/0831
摘要： A processor may operate in one of a plurality of operating states. In a Normal operating state, the processor is not involved with a memory transaction. Upon receipt of a transaction instruction to access a memory location, the processor transitions to a Transaction operating state. In the Transaction operating state, the processor performs changes to a cache line and data associated with the memory location. While in the Transaction operating state, any changes to the data and the cache line is not visible to other processors in the computing system. These changes become visible upon the processor entering a Commit operating state in response to receipt of a commit instruction. After changes become visible, the processor returns to the Normal operating state. If an abort event occurs prior to receipt of the commit instruction, the processor transitions to an Abort operating state where any changes to the data and cache line are discarded.
摘要翻译：处理器可以以多个操作状态中的一个操作。在正常操作状态下，处理器不涉及存储器事务。在接收到访问存储器位置的事务指令时，处理器转换到事务操作状态。在事务操作状态下，处理器执行对高速缓存行的更改和与存储器位置相关联的数据。在事务操作状态下，数据和高速缓存行的任何更改对于计算系统中的其他处理器是不可见的。响应于接收到提交指令，处理器进入提交操作状态时，这些更改变得可见。更改变为可见后，处理器返回到正常运行状态。如果在接收提交指令之前发生中止事件，则处理器转换到中止操作状态，其中对数据和高速缓存行的任何改变被丢弃。

20. 发明授权

US08081526B1 Serialized chip enables 有权
标题翻译：序列化芯片使能
公开(公告)号：US08081526B1
公开(公告)日：2011-12-20
申请号：US12238935
申请日：2008-09-26
申请人： Scott Westbrook , Steven C. Miller
发明人： Scott Westbrook , Steven C. Miller
IPC分类号： G11C7/10
CPC分类号： G11C8/10
摘要： A method and system for serializing an enable signal designating an electronic device such as a chip to enable or disable in order to reduce the number of pins and physical signal traces required to provide connections for enable signals of multiple electronic devices, such as memory, e.g. Flash and DRAM, is described. The enable signal can be encoded to reduce the number of clock cycles to send the serialized enable signal. A device controller can serialize, encode, and send the enable signal to a decoding module using reduced number of pins and physical connections. Then the decoding module can send a decoded enable signals to individual electronic devices or chips to enable or disable.
摘要翻译：串行化指示诸如芯片的电子设备的使能信号的方法和系统，以使能或禁用，以便减少为多个电子设备（例如存储器）的启用信号提供连接所需的引脚数量和物理信号迹线。描述了Flash和DRAM。可以编码使能信号以减少发送串行化使能信号的时钟周期数。设备控制器可以使用减少数量的引脚和物理连接将序列化，编码和发送使能信号发送到解码模块。然后，解码模块可以将解码的使能信号发送到各个电子设备或芯片以启用或禁用。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式