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11. 发明授权

US08288270B2 Enhanced electromigration resistance in TSV structure and design 有权
标题翻译： TSV结构和设计中增强的电迁移阻力
公开(公告)号：US08288270B2
公开(公告)日：2012-10-16
申请号：US13397004
申请日：2012-02-15
申请人： Mukta G Farooq , John A Griesemer , Gary LaFontant , William Francis Landers , Timothy Dooling Sullivan
发明人： Mukta G Farooq , John A Griesemer , Gary LaFontant , William Francis Landers , Timothy Dooling Sullivan
IPC分类号： H01L21/4763
CPC分类号： H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： The embodiments provide a method for reducing electromigration in a circuit containing a through-silicon via (TSV) and the resulting novel structure for the TSV. A TSV is formed through a semiconductor substrate. A first end of the TSV connects to a first metallization layer on a device side of the semiconductor substrate. A second end of the TSV connects to a second metallization layer on a grind side of the semiconductor substrate. A first flat edge is created on the first end of the TSV at the intersection of the first end of the TSV and the first metallization layer. A second flat edge is created on the second end of the TSV at the intersection of the second end of the TSV and the second metallization layer. On top of the first end a metal contact grid is placed, having less than eighty percent metal coverage.
摘要翻译：这些实施例提供了一种用于减少包含硅通孔（TSV）的电路中的电迁移的方法以及用于TSV的所得新颖结构。通过半导体衬底形成TSV。 TSV的第一端连接到半导体衬底的器件侧上的第一金属化层。 TSV的第二端连接到半导体衬底的研磨侧的第二金属化层。在TSV的第一端和第一金属化层的交叉点的TSV的第一端上形成第一平坦边缘。在TSV的第二端和第二金属化层的交叉点的TSV的第二端上形成第二平坦边缘。在第一端的顶部放置金属接触网格，金属覆盖率低于百分之八十。

12. 发明申请

US20120199975A1 ENHANCED ELECTROMIGRATION RESISTANCE IN TSV STRUCTURE AND DESIGN 有权
公开(公告)号：US20120199975A1
公开(公告)日：2012-08-09
申请号：US13023743
申请日：2011-02-09
申请人： Mukta G. Farooq , John A. Griesemer , Gary LaFontant , William Francis Landers , Timothy Dooling Sullivan
发明人： Mukta G. Farooq , John A. Griesemer , Gary LaFontant , William Francis Landers , Timothy Dooling Sullivan
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： The embodiments provide a method for reducing electromigration in a circuit containing a through-silicon via (TSV) and the resulting novel structure for the TSV. A TSV is formed through a semiconductor substrate. A first end of the TSV connects to a first metallization layer on a device side of the semiconductor substrate. A second end of the TSV connects to a second metallization layer on a grind side of the semiconductor substrate. A first flat edge is created on the first end of the TSV at the intersection of the first end of the TSV and the first metallization layer. A second flat edge is created on the second end of the TSV at the intersection of the second end of the TSV and the second metallization layer. On top of the first end a metal contact grid is placed, having less than eighty percent metal coverage.

13. 发明授权

US5711858A Process for depositing a conductive thin film upon an integrated circuit substrate 失效
标题翻译：在集成电路基板上沉积导电薄膜的工艺
公开(公告)号：US5711858A
公开(公告)日：1998-01-27
申请号：US496999
申请日：1995-06-30
申请人： Richard Steven Kontra , Thomas John Licata , James Gardner Ryan , Timothy Dooling Sullivan
发明人： Richard Steven Kontra , Thomas John Licata , James Gardner Ryan , Timothy Dooling Sullivan
IPC分类号： C23C14/04 , C23C14/18 , C23C14/34 , H01L21/768 , H01L23/532
CPC分类号： H01L23/53219 , C23C14/046 , C23C14/185 , C23C14/34 , H01L21/76877 , H01L2924/0002
摘要： An improved process for depositing a conductive thin film upon an integrated circuit substrate by collimated sputtering is disclosed. The sputtered films are alloys of aluminum; a preferred alloying metal is magnesium. The sputtered films of the invention have a more uniform orientation of grains than sputtered aluminum copper silicon alloy films. Such processes are especially useful in the fabrication of integrated circuit devices having aluminum alloy wiring elements.
摘要翻译：公开了一种通过准直溅射在集成电路基板上沉积导电薄膜的改进方法。溅射膜是铝合金; 优选的合金金属是镁。本发明的溅射膜具有比溅射的铝铜硅合金膜更均匀的晶粒取向。这种方法在具有铝合金布线元件的集成电路器件的制造中特别有用。

14. 发明授权

US09105465B2 Wafer edge conditioning for thinned wafers 有权
标题翻译：用于薄晶片的晶圆边缘调节
公开(公告)号：US09105465B2
公开(公告)日：2015-08-11
申请号：US13053803
申请日：2011-03-22
申请人： Timothy Harrison Daubenspeck , Jeffrey P. Gambino , Christopher David Muzzy , Wolfgang Sauter , Timothy Dooling Sullivan
发明人： Timothy Harrison Daubenspeck , Jeffrey P. Gambino , Christopher David Muzzy , Wolfgang Sauter , Timothy Dooling Sullivan
IPC分类号： H01L29/02 , H01L21/02
CPC分类号： H01L21/02021
摘要： The present invention relates to a method for minimizing breakage of wafers during or after a wafer thinning process. A method of forming a rounded edge to the portion of a wafer remaining after surface grinding process is provided. The method comprises providing a semiconductor wafer having an edge and forming a recess in the edge of the wafer using any suitable mechanical or chemical process. The method further comprises forming a substantially continuous curved shape for at least the edge of the wafer located above the recess. Advantageously, the shape of the wafer is formed prior to the backside grind process to prevent problems caused by the otherwise presence of a sharp edge during the backside grind process.
摘要翻译：本发明涉及一种在晶圆薄化过程中或之后使晶片断裂最小化的方法。提供了在表面研磨处理之后残留的晶片部分形成圆形边缘的方法。该方法包括提供具有边缘的半导体晶片，并且使用任何合适的机械或化学过程在晶片的边缘中形成凹陷。该方法还包括形成至少位于凹部上方的晶片的边缘的基本连续的弯曲形状。有利地，在背面研磨处理之前形成晶片的形状，以防止在背面研磨过程期间另外存在锋利边缘引起的问题。

15. 发明授权

US08288747B2 Optoelectronic memory devices 有权
标题翻译：光电存储器件
公开(公告)号：US08288747B2
公开(公告)日：2012-10-16
申请号：US12842158
申请日：2010-07-23
申请人： Fen Chen , Richard Steven Kontra , Tom C. Lee , Theodore M. Levin , Christopher David Muzzy , Timothy Dooling Sullivan
发明人： Fen Chen , Richard Steven Kontra , Tom C. Lee , Theodore M. Levin , Christopher David Muzzy , Timothy Dooling Sullivan
IPC分类号： H01L29/00 , H01L47/00
CPC分类号： G11C13/0009 , G11C13/0004 , G11C13/004 , G11C13/04 , G11C13/047 , G11C2013/0054 , H01L45/1213 , H01L45/145
摘要： A structure. The structure includes a substrate, a resistive/reflective region on the substrate, and a light source/light detecting and/or a sens-amp circuit configured to ascertain a reflectance and/or resistance change in the resistive/reflective region. The resistive/reflective region includes a material having a characteristic of the material's reflectance and/or resistance being changed due to a phase change in the material. The resistive/reflective region is configured to respond, to an electric current through the resistive/reflective region and/or a laser beam projected on the resistive/reflective region, by the phase change in the material which causes a reflectance and/resistance change in the resistive/reflective region from a first reflectance and/or resistance value to a second reflectance and/or resistance value different from the first reflectance and/or resistance value.
摘要翻译：一个结构。该结构包括衬底，衬底上的电阻/反射区域以及被配置为确定电阻/反射区域中的反射率和/或电阻变化的光源/光检测和/或感测放大器电路。电阻/反射区域包括具有材料的反射率和/或电阻的特性的材料由于材料的相变而改变。电阻/反射区域被配置为通过材料的相变来响应通过电阻/反射区域的电流和/或投射在电阻/反射区域上的激光束，这导致反射和/ 电阻/反射区域从第一反射率和/或电阻值到不同于第一反射率和/或电阻值的第二反射率和/或电阻值。

16. 发明授权

US08237288B1 Enhanced electromigration resistance in TSV structure and design 有权
公开(公告)号：US08237288B1
公开(公告)日：2012-08-07
申请号：US13023743
申请日：2011-02-09
申请人： Mukta G Farooq , John A Griesemer , Gary LaFontant , William Francis Landers , Timothy Dooling Sullivan
发明人： Mukta G Farooq , John A Griesemer , Gary LaFontant , William Francis Landers , Timothy Dooling Sullivan
IPC分类号： H01L23/48
CPC分类号： H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： The embodiments provide a method for reducing electromigration in a circuit containing a through-silicon via (TSV) and the resulting novel structure for the TSV. A TSV is formed through a semiconductor substrate. A first end of the TSV connects to a first metallization layer on a device side of the semiconductor substrate. A second end of the TSV connects to a second metallization layer on a grind side of the semiconductor substrate. A first flat edge is created on the first end of the TSV at the intersection of the first end of the TSV and the first metallization layer. A second flat edge is created on the second end of the TSV at the intersection of the second end of the TSV and the second metallization layer. On top of the first end a metal contact grid is placed, having less than eighty percent metal coverage.

17. 发明申请

US20090212431A1 THERMALLY PROGRAMMABLE ANTI-REVERSE ENGINEERING INTERCONNECTS AND METHODS OF FABRICATING SAME 失效
标题翻译：可逆编程的反向工程互连及其制造方法
公开(公告)号：US20090212431A1
公开(公告)日：2009-08-27
申请号：US12035448
申请日：2008-02-22
申请人： Fen Chen , Cathryn Jeanne Christiansen , Michael Anthony Shinosky , Timothy Dooling Sullivan
发明人： Fen Chen , Cathryn Jeanne Christiansen , Michael Anthony Shinosky , Timothy Dooling Sullivan
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76895 , H01L23/34 , H01L23/522 , H01L23/576 , H01L2924/0002 , Y10S438/917 , H01L2924/00
摘要： An interconnect and method of making the interconnect. The method includes forming a dielectric layer on a substrate, the dielectric layer having a top surface and a bottom surface; forming a first wire and a second wire in the dielectric layer, the first wire separated from the second wire by a region of the dielectric layer; and forming metallic nanoparticles in or on the top surface of the dielectric layer between the first and second wires, the metallic nanoparticles capable of electrically connecting the first wire and the second wire only while the nanoparticles are heated to a temperature greater than room temperature and a voltage is applied between the first and second wires.
摘要翻译：互连和互连方法。该方法包括在基底上形成电介质层，介电层具有顶表面和底表面; 在所述电介质层中形成第一线和第二线，所述第一线与所述第二线分离，通过所述介电层的区域; 并且在第一和第二布线之间的电介质层的顶表面中或上方形成金属纳米颗粒，仅在将纳米颗粒加热到大于室温的温度时能够电连接第一布线和第二布线的金属纳米颗粒，在第一和第二导线之间施加电压。

18. 发明申请

US20120287707A1 OPTOELECTRONIC MEMORY DEVICES 审中-公开
标题翻译：光电存储器件
公开(公告)号：US20120287707A1
公开(公告)日：2012-11-15
申请号：US13558541
申请日：2012-07-26
申请人： Fen Chen , Richard Steven Kontra , Tom C. Lee , Theodore M. Levin , Christopher David Muzzy , Timothy Dooling Sullivan
发明人： Fen Chen , Richard Steven Kontra , Tom C. Lee , Theodore M. Levin , Christopher David Muzzy , Timothy Dooling Sullivan
IPC分类号： G11C11/00 , H01L45/00
CPC分类号： G11C13/0009 , G11C13/0004 , G11C13/004 , G11C13/04 , G11C13/047 , G11C2013/0054 , H01L45/1213 , H01L45/145
摘要： A structure. The structure includes a substrate, a resistive/reflective region on the substrate, and a light source/light detecting and/or a sens-amp circuit configured to ascertain a reflectance and/or resistance change in the resistive/reflective region. The resistive/reflective region includes a material having a characteristic of the material's reflectance and/or resistance being changed due to a phase change in the material. The resistive/reflective region is configured to respond, to an electric current through the resistive/reflective region and/or a laser beam projected on the resistive/reflective region, by the phase change in the material which causes a reflectance and/resistance change in the resistive/reflective region from a first reflectance and/or resistance value to a second reflectance and/or resistance value different from the first reflectance and/or resistance value.
摘要翻译：一个结构。该结构包括衬底，衬底上的电阻/反射区域以及被配置为确定电阻/反射区域中的反射率和/或电阻变化的光源/光检测和/或感测放大器电路。电阻/反射区域包括具有材料的反射率和/或电阻的特性的材料由于材料的相变而改变。电阻/反射区域被配置为通过材料的相变来响应通过电阻/反射区域的电流和/或投射在电阻/反射区域上的激光束，这导致反射和/ 电阻/反射区域从第一反射率和/或电阻值到不同于第一反射率和/或电阻值的第二反射率和/或电阻值。

19. 发明申请

US20120241916A1 WAFER EDGE CONDITIONING FOR THINNED WAFERS 有权
标题翻译：用于薄膜波纹的边缘调节
公开(公告)号：US20120241916A1
公开(公告)日：2012-09-27
申请号：US13053803
申请日：2011-03-22
申请人： Timothy Harrison Daubenspeck , Jeffrey P. Gambino , Christopher David Muzzy , Wolfgang Sauter , Timothy Dooling Sullivan
发明人： Timothy Harrison Daubenspeck , Jeffrey P. Gambino , Christopher David Muzzy , Wolfgang Sauter , Timothy Dooling Sullivan
IPC分类号： H01L29/02 , H01L21/302
CPC分类号： H01L21/02021
摘要： The present invention relates to a method for minimizing breakage of wafers during or after a wafer thinning process. A method of forming a rounded edge to the portion of a wafer remaining after surface grinding process is provided. The method comprises providing a semiconductor wafer having an edge and forming a recess in the edge of the wafer using any suitable mechanical or chemical process. The method further comprises forming a substantially continuous curved shape for at least the edge of the wafer located above the recess. Advantageously, the shape of the wafer is formed prior to the backside grind process to prevent problems caused by the otherwise presence of a sharp edge during the backside grind process.
摘要翻译：本发明涉及一种在晶圆薄化过程中或之后使晶片断裂最小化的方法。提供了在表面研磨处理之后残留的晶片部分形成圆形边缘的方法。该方法包括提供具有边缘的半导体晶片，并且使用任何合适的机械或化学过程在晶片的边缘中形成凹陷。该方法还包括形成至少位于凹部上方的晶片的边缘的基本连续的弯曲形状。有利地，在背面研磨处理之前形成晶片的形状，以防止在背面研磨过程期间另外存在锋利边缘引起的问题。

20. 发明授权

US07861204B2 Structures including integrated circuits for reducing electromigration effect 有权
标题翻译：包括用于降低电迁移效应的集成电路的结构
公开(公告)号：US07861204B2
公开(公告)日：2010-12-28
申请号：US11960853
申请日：2007-12-20
申请人： Anthony Kendall Stamper , Timothy Dooling Sullivan , Ping-Chuan Wang
发明人： Anthony Kendall Stamper , Timothy Dooling Sullivan , Ping-Chuan Wang
IPC分类号： G06F17/50
CPC分类号： H01L23/53223 , H01L23/528 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A design structure including an integrated circuit for reducing the electromigration effect. The IC includes a substrate and a power transistor which has first and second source/drain regions. The IC further includes first, second, and third electrically conductive line segments being (i) directly above the first source/drain region and (ii) electrically coupled to the first source/drain region through first contact regions and second contact regions, respectively. The first and second electrically conductive line segments (i) reside in a first interconnect layer of the integrated circuit and (ii) run in the reference direction. The IC further includes an electrically conductive line being (i) directly above the first source/drain region, (ii) electrically coupled to the first and second electrically conductive line segments through a first via and a second via, respectively, (iii) resides in a second interconnect layer of the integrated circuit, and (iv) runs in the reference direction.
摘要翻译：一种设计结构，包括用于降低电迁移效应的集成电路。 IC包括具有第一和第二源/漏区的衬底和功率晶体管。 IC还包括第一，第二和第三导电线段，其直接在第一源极/漏极区域的上方，以及（ii）分别通过第一接触区域和第二接触区域电耦合到第一源极/漏极区域。第一和第二导电线段（i）驻留在集成电路的第一互连层中，并且（ii）沿参考方向延伸。 IC还包括导电线，其是（i）直接在第一源极/漏极区域上方，（ii）分别通过第一通孔和第二通孔电耦合到第一和第二导电线段，（iii）驻留在集成电路的第二互连层中，以及（iv）在参考方向上延伸。

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