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11. 发明授权

US07130985B2 Parallel processor executing an instruction specifying any location first operand register and group configuration in two dimensional register file 失效
标题翻译：并行处理器在二维寄存器文件中执行指定任何位置第一操作数寄存器和组配置的指令
公开(公告)号：US07130985B2
公开(公告)日：2006-10-31
申请号：US10284163
申请日：2002-10-31
申请人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
发明人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
IPC分类号： G06F9/345
CPC分类号： G06F9/30098 , G06F9/30036 , G06F9/3013 , G06F9/3885 , H04L29/06 , H04L69/08
摘要： Described herein is a data processor that comprises a register memory and a processor unit. The processor unit simultaneously executes a single instruction on a plurality of operands in the register memory. The plurality of operands may be one or more contiguous regions. The contiguous regions may be specified as an address and a format such as a row, a column, or a neighborhood relative to the address.
摘要翻译：这里描述的是包括寄存器存储器和处理器单元的数据处理器。处理器单元同时对寄存器存储器中的多个操作数执行单个指令。多个操作数可以是一个或多个连续区域。可以将连续区域指定为相对于地址的地址和诸如行，列或邻域的格式。

12. 发明授权

US07069417B2 Vector processing system 有权
公开(公告)号：US07069417B2
公开(公告)日：2006-06-27
申请号：US10284301
申请日：2002-10-31
申请人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
发明人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
IPC分类号： G06F15/80
CPC分类号： G06F9/30036 , G06F9/3842 , G06F9/3885
摘要： A vector processing system for executing vector instructions, each instruction defining multiple value pairs, an operation to be executed and a modifier, the vector processing system comprising a plurality of parallel processing units, each arranged to receive one of said pairs of values and, when selected, to implement an operation on said value pair to generate a result, each processing unit comprising at least one flag and being selectable in dependence on a condition defined by said at least one flag, wherein the modifier defines the condition under which the parallel processing unit is individually selected.

13. 发明申请

US20060095681A1 Narrow/wide cache 有权
标题翻译：窄/宽缓存
公开(公告)号：US20060095681A1
公开(公告)日：2006-05-04
申请号：US11299264
申请日：2005-12-01
申请人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
发明人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
IPC分类号： G06F13/00
CPC分类号： G06F9/3828 , G06F9/30145 , G06F9/30167 , G06F9/3885 , G06F9/3889 , G06F12/0804 , G06F12/0888 , Y02D10/13
摘要： A method for transferring data, between a first device and second device in a core processor including a data cache, comprising the steps of, when said first device supports wide data transfer, and said transfer of data comprises a data write operation from said first device to said second device, writing said data to the second device without writing the data to said data cache.
摘要翻译：一种用于在包括数据高速缓存的核心处理器中的第一设备和第二设备之间传送数据的方法，包括以下步骤：当所述第一设备支持宽数据传输时，所述数据传输包括来自所述第一设备的数据写入操作到所述第二设备，将所述数据写入所述第二设备，而不将数据写入所述数据高速缓存。

14. 发明授权

US06839079B2 Video-telephony system 有权
标题翻译：视频电话系统
公开(公告)号：US06839079B2
公开(公告)日：2005-01-04
申请号：US10284307
申请日：2002-10-31
申请人： Stephen Barlow , Timothy Ramsdale , Robert Swann , Neil Bailey , David Plowman
发明人： Stephen Barlow , Timothy Ramsdale , Robert Swann , Neil Bailey , David Plowman
IPC分类号： H04N7/14
CPC分类号： H04N21/4223 , H04N7/142
摘要： A video-telephony system comprising a plurality of cameras, each capable of generating a video signal; a plurality of display units which are able to receive video signals from the cameras via a wireless link; a plurality of telephones which are able to communicate with each other; means for identifying a camera convenient for a user of a first one of the telephones; and means for transmitting a video signal generated by the camera to a display unit convenient for a user of a second one of the telephones engaged in a call with the first one of the telephones.
摘要翻译：一种包括多个摄像机的视频电话系统，每个摄像机能够产生视频信号; 能够经由无线链路从摄像机接收视频信号的多个显示单元; 能够彼此通信的多个电话机; 用于识别便于第一个电话用户的相机的装置; 以及用于将由所述照相机生成的视频信号发送到便利于与所述第一个所述电话进行呼叫的所述电话中的第二个的用户的显示单元的装置。

15. 发明授权

US07203800B2 Narrow/wide cache 有权
标题翻译：窄/宽缓存
公开(公告)号：US07203800B2
公开(公告)日：2007-04-10
申请号：US11299264
申请日：2005-12-01
申请人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
发明人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
IPC分类号： G06F12/02
CPC分类号： G06F9/3828 , G06F9/30145 , G06F9/30167 , G06F9/3885 , G06F9/3889 , G06F12/0804 , G06F12/0888 , Y02D10/13
摘要： A method for transferring data, between a first device and second device in a core processor including a data cache, comprising the steps of, when said first device supports wide data transfer, and said transfer of data comprises a data write operation from said first device to said second device, writing said data to the second device without writing the data to said data cache.
摘要翻译：一种用于在包括数据高速缓存的核心处理器中的第一设备和第二设备之间传送数据的方法，包括以下步骤：当所述第一设备支持宽数据传输时，所述数据传输包括来自所述第一设备的数据写入操作到所述第二设备，将所述数据写入所述第二设备，而不将数据写入所述数据高速缓存。

16. 发明授权

US07167972B2 Vector/scalar system with vector unit producing scalar result from vector results according to modifier in vector instruction 有权
标题翻译：向量/标量系统，其向量单位根据向量指令中的修饰符从向量结果生成标量
公开(公告)号：US07167972B2
公开(公告)日：2007-01-23
申请号：US10284302
申请日：2002-10-31
申请人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
发明人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
IPC分类号： G06F9/302
CPC分类号： G06F9/30036 , G06F9/30021 , G06F9/3013 , G06F9/30185 , G06F9/3889 , G06F15/8076
摘要： Described herein is a processor for executing instructions and a method therefor. The processor comprises a scalar unit for executing scalar instructions each defining a single value pair; a vector unit for executing vector instructions each defining multiple value pairs; and an instruction decoder for receiving a single stream of instructions including scalar instructions and vector instructions and operable to direct scalar instructions to the scalar unit and vector instructions to the vector unit. The vector unit can comprises a plurality of value processing units and a scalar result unit. The scalar unit can comprise a scalar register file. Communication between the vector unit and the scalar unit is enabled by allowing the vector unit to access the scalar register file and allowing the scalar unit to access output from the scalar result unit. The output of the scalar result unit may be based on the relative magnitudes of outputs from the plurality of value processing units.
摘要翻译：这里描述了一种用于执行指令的处理器及其方法。处理器包括用于执行每个定义单个值对的标量指令的标量单元; 矢量单元，用于执行各自定义多个值对的矢量指令; 以及指令解码器，用于接收包括标量指令和向量指令的单个指令流，并且可操作以将标量指令引导到标量单元，并向矢量单元指示矢量指令。向量单元可以包括多个值处理单元和标量结果单元。标量单元可以包括标量寄存器文件。通过允许向量单元访问标量寄存器文件并允许标量单元访问标量结果单元的输出，可以实现向量单元和标量单元之间的通信。标量结果单元的输出可以基于来自多个值处理单元的输出的相对大小。

17. 发明授权

US07080216B2 Data access in a processor 失效
公开(公告)号：US07080216B2
公开(公告)日：2006-07-18
申请号：US10284164
申请日：2002-10-31
申请人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
发明人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
IPC分类号： G06F12/00
CPC分类号： G06T9/00 , G06F9/30036 , G06F9/30098 , G06F9/3013 , G06F9/30141 , G06F9/30145 , G06F9/30167 , G06F9/345 , G06F9/3836 , G06F9/3885
摘要： A data processor comprising: a register memory comprising an array of memory cells extending in two dimensions, the cells being located on rows in the first dimension and columns in the second dimension, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the row and column of the cell in the array; and a processing unit capable of executing instructions that operate on a plurality of memory cells in the register, the instructions identifying the plurality of cells by means of a first instruction part specifying a pair of coordinates that identify a first cell in the array, and a second instruction part that identifies the configuration of the plurality of cells relative to the first cell; the data processor being arranged to interpret a first form of second instruction part as specifying a first group of cells all of which are located in the same row but in different columns, and to interpret a second form of second instruction part as specifying a first group of cells all of which are located in the same column but in different rows.

18. 发明申请

US20060155925A1 Data access in a processor 有权
公开(公告)号：US20060155925A1
公开(公告)日：2006-07-13
申请号：US11333574
申请日：2006-01-17
申请人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
发明人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
IPC分类号： G06F13/00
CPC分类号： G06T9/00 , G06F9/30036 , G06F9/30098 , G06F9/3013 , G06F9/30141 , G06F9/30145 , G06F9/30167 , G06F9/345 , G06F9/3836 , G06F9/3885
摘要： A data processor comprising: a register memory comprising an array of memory cells extending in two dimensions, the cells being located on rows in the first dimension and columns in the second dimension, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the row and column of the cell in the array; and a processing unit capable of executing instructions that operate on a plurality of memory cells in the register, the instructions identifying the plurality of cells by means of a first instruction part specifying a pair of coordinates that identify a first cell in the array, and a second instruction part that identifies the configuration of the plurality of cells relative to the first cell; the data processor being arranged to interpret a first form of second instruction part as specifying a first group of cells all of which are located in the same row but in different columns, and to interpret a second form of second instruction part as specifying a first group of cells all of which are located in the same column but in different rows.

19. 发明授权

US07036001B2 Vector processing system 有权
公开(公告)号：US07036001B2
公开(公告)日：2006-04-25
申请号：US10284194
申请日：2002-10-31
申请人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
发明人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
IPC分类号： G06F15/80
CPC分类号： G06F15/8092 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F15/8076
摘要： A vector processing system for executing vector instructions, each instruction defining multiple pairs of values, an operation to be executed on each of said value pairs and a scalar modifier, the vector processing system comprising a plurality of parallel processing units, each arranged to receive one of said pairs of values and to implement the defined operation on said value pair to generate a respective result; and a scalar result unit for receiving the results of the parallel processing units and for using said results in a manner defined by the scalar modifier to generate a single output value for said instruction.

20. 发明授权

US07107429B2 Data access in a processor 有权
公开(公告)号：US07107429B2
公开(公告)日：2006-09-12
申请号：US11364927
申请日：2006-03-01
申请人： Stephen Barlow , Timothy Ramsdale , Robert Swann , Nel Bailey , David Plowman
发明人： Stephen Barlow , Timothy Ramsdale , Robert Swann , Nel Bailey , David Plowman
IPC分类号： G06F12/00
CPC分类号： G06F9/3013 , G06F9/30098 , G06F9/30141 , G06F9/30149 , G06F9/30167 , G06F9/3885 , G06F15/8053
摘要： A data processor comprising: a register memory comprising an array of memory cells, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the cell in the array.

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