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    • 13. 发明申请
    • PHASE NOISE MINIMIZED PHASE/FREQUENCY-LOCKED VOLTAGE-CONTROLLED OSCILLATOR CIRCUIT
    • 相位噪声最小相位/频率锁定电压控制振荡器电路
    • US20100033257A1
    • 2010-02-11
    • US12579149
    • 2009-10-14
    • Stefano PelleranoAshoke RaviYorgos Palaskas
    • Stefano PelleranoAshoke RaviYorgos Palaskas
    • H03L7/00
    • H03L7/099H03L7/0995H03L7/18H03L2207/06
    • A phase noise minimization circuit is disclosed, to be used in a voltage-controlled oscillator (VCO) circuit embedded in a feedback system. The phase noise minimization circuit includes a noise power meter to analyze the control voltage fed into the VCO by the feedback system and determine its voltage noise power. Since the VCO is controlled by the feedback system, the control voltage noise power is also an indication of the VCO phase noise power for frequencies offset within the bandwidth of the feedback system. The VCO has several parameters that can be adjusted to affect its phase noise. A minimization algorithm generates the optimum set of parameters that minimize the control voltage noise power (and thus the VCO phase noise power), and sends them to the oscillator. The phase noise minimization circuit may be used in a variety of applications, particularly in phase-locked loop and frequency-locked loop VCOs.
    • 公开了一种用于嵌入在反馈系统中的压控振荡器(VCO)电路中的相位噪声最小化电路。 相位噪声最小化电路包括噪声功率计,用于分析由反馈系统馈送到VCO的控制电压并确定其电压噪声功率。 由于VCO由反馈系统控制,所以控制电压噪声功率也是在反馈系统的带宽内偏移的频率的VCO相位噪声功率的指示。 VCO具有几个参数,可以调整以影响其相位噪声。 最小化算法生成最小化控制电压噪声功率(从而使VCO相位噪声功率)最小化的最佳参数集,并将其发送到振荡器。 相位噪声最小化电路可以用于各种应用中,特别是在锁相环和锁相环VCO中。
    • 14. 发明申请
    • DIGITAL FRACTIONAL FREQUENCY DIVIDER
    • 数字分频分频器
    • US20140185736A1
    • 2014-07-03
    • US13997191
    • 2011-10-01
    • Kailash ChandrashekarStefano Pellerano
    • Kailash ChandrashekarStefano Pellerano
    • H03K21/02
    • H03K21/023H03K21/026H03K23/542
    • A digital fractional frequency divider for fractionally dividing a digital frequency signal can include a plurality of clock division counter modules, a plurality of sampling modules, and a summing module. The plurality of clock division counter modules can each receive an input clock signal that is phase-shifted from a remaining plurality of input clock signals. Each clock division counter module can generate a long periodic pulse from the received input clock signal. Each sampling module can couple to an output of one of the plurality of clock division counter modules and can generate a short periodic pulse from the long periodic pulse. The summing module can sum the plurality of short periodic pulses to generate a fractional frequency clock signal.
    • 用于分数数字频率信号的数字分数分频器可以包括多个时钟分配计数器模块,多个采样模块和求和模块。 多个时钟分配计数器模块可以各自接收从剩余的多个输入时钟信号中相移的输入时钟信号。 每个时钟分配计数器模块可以从接收到的输入时钟信号产生长周期脉冲。 每个采样模块可以耦合到多个时钟分配计数器模块之一的输出,并且可以从长周期脉冲产生短周期脉冲。 求和模块可以对多个短周期脉冲求和以产生分数频率时钟信号。
    • 15. 发明申请
    • Non-backscatter passive RFID
    • 无反向散射无源RFID
    • US20070279225A1
    • 2007-12-06
    • US11443592
    • 2006-05-30
    • Stefano PelleranoJavier AlvaradoYorgos Palaskas
    • Stefano PelleranoJavier AlvaradoYorgos Palaskas
    • G08B13/14
    • G06K19/0723G06K19/0707
    • A radio frequency identification (RFID) system may use passive RFID tags that harvest electrical energy from a received signal and store that harvested electrical energy in a capacitor. The stored electrical energy may then be used to transmit from the RFID tag after the received signal has stopped. To decrease the size of the capacitor that is needed, the RFID tag may transmit only briefly, and then use a subsequent received signal to charge up the capacitor for another brief transmission. In some embodiments, each transmission only represents a single binary bit, but a series of such transmissions may be used to transmit multiple bits. Some embodiments may use a radio frequency of 10's of gigahertz.
    • 射频识别(RFID)系统可以使用无源RFID标签,其从接收到的信号中收集电能并将收集的电能存储在电容器中。 然后,所存储的电能可以在接收信号停止之后用于从RFID标签发送。 为了减小所需的电容器的尺寸,RFID标签可以仅短暂地传输,然后使用随后的接收信号对电容器充电以进行另一短暂的传输。 在一些实施例中,每个传输仅表示单个二进制位,但是可以使用一系列这样的传输来传输多个位。 一些实施例可以使用千兆赫兹的10的射频。
    • 17. 发明授权
    • Device, system and method of delay calibration
    • 延迟校准的装置,系统和方法
    • US07605625B2
    • 2009-10-20
    • US11868500
    • 2007-10-07
    • Stefano PelleranoGeorgios Palaskas
    • Stefano PelleranoGeorgios Palaskas
    • H03L7/08H03L7/06
    • H03L7/0812H03L7/07
    • System and method of calibrating delay mismatch for high-spectral purity applications. For example, a method includes measuring the delay of one delay element at a time in a fixed topology by moving a time reference generated by an auxiliary delay-locked loop. The auxiliary DLL may have a replica structure of the primary DLL being calibrated. The calibration method uses one output clock signal of the primary DLL and measures delay mismatch using a reference phase previously measured using the same topology. The calibration method takes into account all delay mismatches in the topology up to the primary DLL output clock signal, including any delay generated by an associated multiplexer.
    • 用于校准高光谱纯度应用的延迟失配的系统和方法。 例如,一种方法包括通过移动由辅助延迟锁定环产生的时间参考来测量固定拓扑中的一个延迟元件的延迟。 辅助DLL可以具有被校准的主DLL的复制结构。 校准方法使用主DLL的一个输出时钟信号,并使用先前使用相同拓扑结构测量的参考相位来测量延迟失配。 校准方法考虑到拓扑中的所有延迟不匹配,直到主DLL输出时钟信号,包括由相关联的多路复用器产生的任何延迟。
    • 18. 发明申请
    • DEVICE, SYSTEM AND METHOD OF DELAY CALIBRATION
    • 装置,系统和延迟校准方法
    • US20090091362A1
    • 2009-04-09
    • US11868500
    • 2007-10-07
    • Stefano PelleranoGeorgios Palaskas
    • Stefano PelleranoGeorgios Palaskas
    • H03L7/08
    • H03L7/0812H03L7/07
    • System and method of calibrating delay mismatch for high-spectral purity applications. For example, a method includes measuring the delay of one delay element at a time in a fixed topology by moving a time reference generated by an auxiliary delay-locked loop. The auxiliary DLL may have a replica structure of the primary DLL being calibrated. The calibration method uses one output clock signal of the primary DLL and measures delay mismatch using a reference phase previously measured using the same topology. The calibration method takes into account all delay mismatches in the topology up to the primary DLL output clock signal, including any delay generated by an associated multiplexer.
    • 用于校准高光谱纯度应用的延迟失配的系统和方法。 例如,一种方法包括通过移动由辅助延迟锁定环产生的时间参考来测量固定拓扑中的一个延迟元件的延迟。 辅助DLL可以具有被校准的主DLL的复制结构。 校准方法使用主DLL的一个输出时钟信号,并使用先前使用相同拓扑结构测量的参考相位来测量延迟失配。 校准方法考虑到拓扑中的所有延迟不匹配,直到主DLL输出时钟信号,包括由相关联的多路复用器产生的任何延迟。