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11. 发明申请

US20100232803A1 Integrated Equalizer and Michelson Interferometer Structure for Inter-Symbol Interference-Suppressed colorless DPSK demodulation 有权
标题翻译：用于符号间干扰抑制无色DPSK解调的集成均衡器和迈克尔逊干涉仪结构
公开(公告)号：US20100232803A1
公开(公告)日：2010-09-16
申请号：US12731869
申请日：2010-03-25
申请人： Philip Nan Ji , Lei Xu , Ting Wang , Shuji Murakami , Tsutomu Tajima , Yutaka Yano
发明人： Philip Nan Ji , Lei Xu , Ting Wang , Shuji Murakami , Tsutomu Tajima , Yutaka Yano
IPC分类号： H04B10/12
CPC分类号： H04B10/677
摘要： An optical device includes an interferometer for a received optical differential phase shift keying DPSK signal, and an equalizer integrated with the interferometer in a manner for reducing from optical filtering effects an interference by signal bits of the DPSK signal with signal bits of a contiguous DPSK signal. The interferometer is a Michelson delay interferometer type, but can also be a Mach-Zehnder delay interferometer type on fiber, waveguide or other optical structure. The equalizer is a Fabry-Perot type equalizer, but can be a ring resonator type or a fiber based equalizer.
摘要翻译：光学装置包括用于接收的光学差分相移键控DPSK信号的干涉仪，以及与干涉仪集成的均衡器，以减少光学滤波的方式，利用DPSK信号的信号位与相邻DPSK信号的信号位的干扰。干涉仪是迈克尔逊延迟干涉仪型号，但也可以是光纤，波导或其他光学结构上的马赫 - 曾德延迟干涉仪。均衡器是法布里 - 珀罗型均衡器，但可以是环形谐振器型或基于光纤的均衡器。

12. 发明授权

US06678317B1 Adaptive equalizer device and method for controlling adaptive equalizer 失效
标题翻译：自适应均衡器装置及自适应均衡器控制方法
公开(公告)号：US06678317B1
公开(公告)日：2004-01-13
申请号：US09256175
申请日：1999-02-24
申请人： Shuji Murakami , Kazuya Yamanaka , Hiroyuki Mizutani
发明人： Shuji Murakami , Kazuya Yamanaka , Hiroyuki Mizutani
IPC分类号： H03H730
CPC分类号： H04L25/03038 , H04L2025/03726
摘要： An object is to obtain an adaptive equalizer device and an adaptive equalizer controlling method which provide an ideal output signal certainly and in a shorter time. The adaptive equalizer device includes an adaptive equalizer (4a) receiving a signal indicating a symbol, for filtering the signal indicating the symbol to adaptively remove intersymbol interference by selectively using one of a plurality of preset algorithms, and a rotation detecting circuit (19) receiving an output signal (y(n)) from the adaptive equalizer, for detecting rotation of the symbol of the output signal (y(n)), wherein the adaptive equalizer (4a) selects one of the plurality of algorithms in accordance with detected result flags (&agr;, &bgr;) from the rotation detecting circuit (19).
摘要翻译：本发明的目的是获得一种自适应均衡器装置和一种自适应均衡器控制方法，其可以在更短的时间内提供理想的输出信号。自适应均衡器装置包括：自适应均衡器（4a），其接收指示符号的信号，用于通过选择性地使用多个预设算法之一来过滤指示符号的信号以自适应地去除符号间干扰;以及旋转检测电路（19）来自所述自适应均衡器的输出信号（y（n）），用于检测所述输出信号（y（n））的符号的旋转，其中所述自适应均衡器（4a）根据检测结果选择所述多个算法中的一个来自旋转检测电路（19）的标志（α，β）。

13. 发明授权

US06338940B1 Silver halide photographic light sensitive materials and image forming method by use thereof 失效
标题翻译：卤化银照相感光材料及其使用的成像方法
公开(公告)号：US06338940B1
公开(公告)日：2002-01-15
申请号：US09330943
申请日：1999-06-11
申请人： Kazuhiro Miyazawa , Junji Ito , Yumiko Nimura , Shinichi Suzuki , Makoto Kaga , Shuji Murakami
发明人： Kazuhiro Miyazawa , Junji Ito , Yumiko Nimura , Shinichi Suzuki , Makoto Kaga , Shuji Murakami
IPC分类号： G03C1005
CPC分类号： G03C1/015 , G03C7/3022 , G03C7/3041 , G03C2001/0153 , G03C2001/03517 , G03C2200/26
摘要： A silver halide photographic light sensitive material IS DISCLOSED, comprising a support having thereon a yellow dye image forming layer, a magenta dye image forming layer and a cyan dye image forming layer, wherein when the photographic material is subjected to exposure of not more than 10−3 sec. per pixel element and further to color developing to form yellow, magenta and cyan images, a variation at multiple exposure, based on non-multiple exposure, of an average gradation, which is a slope that connects two pints corresponding to densities of 0.5 and 1.5 on a characteristic curve of each of the yellow, magenta and cyan images, is not more than 10%.
摘要翻译：公开了一种卤化银照相感光材料，其包括其上具有黄色染料图像形成层，品红色染料图像形成层和青色染料图像形成层的载体，其中当照相材料经受不超过10 -3秒并且进一步显色以形成黄色，品红色和青色图像，基于非多次曝光的多次曝光的变化，平均灰度是连接对应于0.5和1.5的密度的两个品脱的斜率在每个黄色，品红色和青色图像的特征曲线上，不大于10％。

14. 发明授权

US06311203B1 Multiplier, and fixed coefficient FIR digital filter having plural multipliers 失效
标题翻译：具有多个乘法器的乘法器和固定系数FIR数字滤波器
公开(公告)号：US06311203B1
公开(公告)日：2001-10-30
申请号：US09203373
申请日：1998-12-02
申请人： Yasushi Wada , Shuji Murakami
发明人： Yasushi Wada , Shuji Murakami
IPC分类号： G06F752
CPC分类号： H03H17/06 , G06F7/523
摘要： A multiplication device for performing a multiplication operation on a multiplicand X and two fixed coefficients C1 and C2 where C1>C2. The multiplication device comprises a multiplier for multiplying multiplicand X and the average CA of the two fixed coefficients C1 and C2; a shift register for obtaining a sum of the multiplicand X data after being shifted up according to a position of a “1” bit in bit data where the bit data is the remainder coefficient obtained by subtracting average CA from fixed coefficient C1; and a selector for selecting a product obtained for one of the fixed coefficients C1 and C2. When the fixed coefficient C1 is selected, the selector outputs the sum of the product returned by the multiplier and the accumulated value obtained by the shift register; when fixed coefficient C2 is selected, the selector outputs the difference of the product returned by the multiplier minus the accumulated value obtained by the shift register. A fixed coefficient FIR digital filter having a plurality of multiplication devices above-mentioned is also disclosed.
摘要翻译：用于对被乘数X和两个固定系数C1和C2执行乘法运算的乘法装置，其中C1> C2。乘法装置包括用于将被乘数X与两个固定系数C1和C2的平均CA相乘的乘法器; 移位寄存器，用于根据比特数据中的“1”位的位置向上移位被乘数X数据，其中比特数据是通过从固定系数C1减去平均CA而获得的余数系数; 以及选择器，用于选择为固定系数C1和C2之一获得的乘积。当选择固定系数C1时，选择器输出由乘法器返回的乘积和由移位寄存器获得的累加值之和; 当选择固定系数C2时，选择器输出由乘数返回的乘积的差值减去由移位寄存器获得的累加值。还公开了具有上述多个乘法装置的固定系数FIR数字滤波器。

15. 发明授权

US5301155A Multiblock semiconduction storage device including simultaneous operation of a plurality of block defect determination circuits 失效
标题翻译：多块半导体存储装置，包括多个块缺陷确定电路的同时操作
公开(公告)号：US5301155A
公开(公告)日：1994-04-05
申请号：US670811
申请日：1991-03-18
申请人： Tomohisa Wada , Shuji Murakami
发明人： Tomohisa Wada , Shuji Murakami
IPC分类号： G11C29/28 , G11C29/40 , G11C29/00
CPC分类号： G11C29/40 , G11C29/28
摘要： A semiconductor storage device including a plurality of blocks each having an array of memory cells includes an exclusive OR circuit provided in each of the plurality of blocks for making a determination as to whether data written in memory cells in the blocks are normally read. Exclusive OR circuits of a plurality of memory cell array blocks are connected to an OR circuit. With an output signal from the OR circuit, a determination is made as to whether a plurality of memory cell array blocks are normal or not. Since test data from a plurality of memory cell array blocks are simultaneously examined by an OR circuit, a test time for the semiconductor storage device can be reduced.
摘要翻译：包括具有存储单元阵列的多个块的半导体存储装置包括设置在多个块中的每一个块中的异或电路，用于确定写入块中的存储单元的数据是否被正常读取。多个存储单元阵列块的异或电路连接到OR电路。利用来自OR电路的输出信号，确定多个存储单元阵列块是否正常。由于来自多个存储单元阵列块的测试数据由OR电路同时检查，所以可以减少半导体存储器件的测试时间。

16. 发明授权

US5248946A Symmetrical differential amplifier circuit 失效
标题翻译：对称差分放大器电路
公开(公告)号：US5248946A
公开(公告)日：1993-09-28
申请号：US805144
申请日：1991-12-11
申请人： Shuji Murakami , Atsushi Ohba , Kenji Anami
发明人： Shuji Murakami , Atsushi Ohba , Kenji Anami
IPC分类号： G11C11/419 , H03F3/34 , H03F3/347 , H03F3/45
CPC分类号： H03F3/45076
摘要： An amplifier circuit of a symmetrical type is implemented with load transistors 1, 3, 5, 6 and input transistors 2, 4. Load transistors 1, 5 and input transistor 2 constitute a first inverter, and load transistors 3, 6 and input transistor 4 constitute a second inverter. A change in the output potential of each inverter is transmitted to a load transistor of the other inverter and increases the fluctuation of the potential of an output signal. A transistor 9 or 10 for current control is arranged between an input transistor and ground or between a load transistor and a power supply. The transistor 9 or 10 for current control interrupts through current when operation of the amplifier circuit is unnecessary and enhances the gain when the amplifier circuit is on operation. The gain is enhanced by setting the conductance of the load transistor and the conductance of the input transistor on predetermined conditions. Furthermore, an offset voltage caused in each amplifier circuit is canceled out by connecting two sets of symmetrical-type amplifier circuits.

17. 发明授权

US5192352A Molding method using glass blank 失效
标题翻译：使用玻璃毛坯的成型方法
公开(公告)号：US5192352A
公开(公告)日：1993-03-09
申请号：US731319
申请日：1991-07-17
申请人： Tetsuo Kuwabara , Shuji Murakami
发明人： Tetsuo Kuwabara , Shuji Murakami
IPC分类号： C03B40/02 , C03B11/00 , C03B11/08 , C03C17/02
CPC分类号： C03C17/02 , C03B11/08 , Y10S425/808
摘要： The present invention relates to a glass blank for producing optical element used for the press molding thereof, having a core glass and a surface layer covering at least the optically functional surface of the core glass. The surface layer consists of an evaporation glass. This invention also relates to the technique to mold a glass lens using the glass blank.
摘要翻译：本发明涉及一种用于压制成型的用于制造光学元件的玻璃坯料，其具有芯玻璃和至少覆盖芯玻璃的光学功能表面的表面层。表层由蒸发玻璃组成。本发明还涉及使用玻璃坯料来模制玻璃透镜的技术。

18. 发明授权

US5019883A Input protective apparatus of semiconductor device 失效
标题翻译：半导体器件输入保护装置
公开(公告)号：US5019883A
公开(公告)日：1991-05-28
申请号：US443864
申请日：1989-11-30
申请人： Shigeru Mori , Michihiro Yamada , Hideshi Miyatake , Shuji Murakami
发明人： Shigeru Mori , Michihiro Yamada , Hideshi Miyatake , Shuji Murakami
IPC分类号： H01L29/78 , H01L21/8234 , H01L23/64 , H01L27/02 , H01L27/06 , H01L27/088 , H02H7/20
CPC分类号： H02H7/20 , H01L23/647 , H01L27/0251 , H01L2924/0002 , H01L2924/3011
摘要： An input protective apparatus for a semiconductor device (Q3) comprises an MOS transistor (Q4) having a thick gate insulating film formed therein. The MOS transistor (Q4) has one active layer connected to an input terminal (11) through a second resistor element (R2) and connected to a semiconductor device (Q3) to be protected through a first resistor element (R1), and an other active layer connected to a ground terminal. The input protective apparatus is adapted such that a resistance value R.sub.1 of a first resistor element (R1) and a resistance value R.sub.2 of the second resistor element (R2) satisfy the relation R.sub.1 >R.sub.2, and the on-resistance R.sub.3 of the MOS transistor (Q4) and the resistance value R.sub.2 satisfy the relation R.sub.3
摘要翻译：一种用于半导体器件（Q3）的输入保护装置包括其中形成有厚栅极绝缘膜的MOS晶体管（Q4）。 MOS晶体管（Q4）具有通过第二电阻元件（R2）连接到输入端子（11）并且连接到半导体器件（Q3）的一个有源层，以通过第一电阻元件（R1）被保护，另一个有源层连接到接地端子。输入保护装置适于使得第一电阻元件（R1）的电阻值R1和第二电阻元件（R2）的电阻值R2满足关系R1> R2，并且MOS晶体管的导通电阻R3 （Q4），电阻值R2满足R3 << R2的关系。

19. 发明申请

US20120066384A1 HOME APPLIANCE MONITORING SYSTEM 有权
标题翻译：家用电器监控系统
公开(公告)号：US20120066384A1
公开(公告)日：2012-03-15
申请号：US13320147
申请日：2010-05-11
申请人： Tomoyuki Hatanaka , Osamu Sekine , Shuji Murakami , Hiroyasu Nakanishi
发明人： Tomoyuki Hatanaka , Osamu Sekine , Shuji Murakami , Hiroyasu Nakanishi
IPC分类号： G06F15/173
CPC分类号： H04L12/2823
摘要： A home appliance monitoring system includes: a plurality of home systems respectively including a central managing device configured to collect monitoring information from a home appliance; and a center server connected to the central managing device of each home system. The center server calculates the current load amount, and sends an activating instruction signal or a deactivating instruction signal to each central managing device on the basis of the current load amount. The central managing device sets its communication status to an activated status in response to receiving the activating instruction signal, and sets its communication status to a deactivated status in response to receiving the deactivating instruction signal. The home system stores the monitoring information while the communication status is the deactivated status. The home system sends the stored monitoring information to the center server when the communication status is switched from the deactivated status to the activated status. The home system sends the monitoring information to the center server while the communication status is the activated status. The center server stores the monitoring information received from the home system.
摘要翻译：家用电器监控系统包括：多个家庭系统，分别包括中央管理装置，其被配置为收集来自家用电器的监控信息; 连接到每个家庭系统的中央管理设备的中心服务器。中心服务器计算当前负载量，并根据当前负载量向每个中央管理设备发送激活指令信号或去激活指令信号。中央管理装置响应于接收到激活指令信号将其通信状态设置为激活状态，并且响应于接收到去激活指令信号将其通信状态设置为去激活状态。家庭系统存储监视信息，而通信状态为停用状态。当通信状态从禁用状态切换到激活状态时，家庭系统将存储的监控信息发送到中心服务器。通信状态为激活状态时，家庭系统将监控信息发送给中心服务器。中心服务器存储从家庭系统接收到的监控信息。

20. 发明授权

US08064768B2 Intra-channel equalizing optical interleaver 有权
标题翻译：信道内均衡光交织器
公开(公告)号：US08064768B2
公开(公告)日：2011-11-22
申请号：US12128748
申请日：2008-05-29
申请人： Philip Nan Ji , Lei Xu , Ting Wang , Shuji Murakami , Tsutomu Tajima , Yutaka Yano
发明人： Philip Nan Ji , Lei Xu , Ting Wang , Shuji Murakami , Tsutomu Tajima , Yutaka Yano
IPC分类号： H04J14/02
CPC分类号： G02B6/29386 , G02B6/29335 , G02B6/2935 , G02B6/29358 , H04B10/25073 , H04J14/02
摘要： An apparatus includes an interleaver configuration for at least one of combining or separating odd and even channel groups to achieve channel density doubling; and an optical equalizer for suppressing inter symbol interference within the channels to provide intra-channel equalizing in the optical path, the equalizer being integrated into the interleaver. Preferably, optical equalizer and interleaver are integrated together as a single monolithic device, the optical equalizer includes a passband that has a dip in the channel center to achieve a raised-cosine filtering profile in the optical signal path to achieve inter-symbol interference ISI suppression, and the equalizer includes integration into the optical path of the interleaver to realize a monolithic device combining or separating odd and even channel groups to achieve channel density doubling. Preferably, also, the optical equalizer includes a first equalizer with half the depth of required ripple dips at both a first output port and an input port and a second equalizer with half the depth of required ripple dips at a second output port.
摘要翻译：一种装置包括用于组合或分离奇数和偶数信道组中的至少一个的交织器配置，以实现信道密度倍增; 以及光学均衡器，用于抑制信道内的符号间干扰，以在光路中提供信道间均衡，均衡器被集成到交织器中。优选地，光学均衡器和交织器作为单个单片器件集成在一起，光学均衡器包括通道，该通带在信道中心具有下降以在光信号路径中实现升余弦滤波曲线，以实现符号间干扰ISI抑制并且均衡器包括集成到交织器的光路中，以实现组合或分离奇数和偶数信道组的单片设备，以实现信道密度加倍。优选地，光学均衡器还包括第一均衡器，其具有在第一输出端口和输入端口处的所需波纹下降的一半深度，以及在第二输出端口处具有所需纹波下降的一半深度的第二均衡器。

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