专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20130202064A1 ERROR SIGNATURE ANALYSIS FOR DATA AND CLOCK RECOVERY IN A COMMUNICATION SYSTEM 有权
标题翻译：通信系统中数据和时钟恢复的错误签名分析
公开(公告)号：US20130202064A1
公开(公告)日：2013-08-08
申请号：US13368314
申请日：2012-02-07
申请人： Erik V. Chmelar
发明人： Erik V. Chmelar
IPC分类号： H04L27/06
CPC分类号： H04L25/03057
摘要： Described embodiments recover timing and data information from a signal received via a communication channel. An analog-to-digital converter (ADC) operating at a baud rate of the communication channel generates an actual ADC value corresponding to each bit sample of the received signal. A fast symbol estimation module estimates, based on the actual ADC value, a bit value corresponding to each bit sample. The fast symbol estimation module operates at a digital clock rate. The estimated bit values are provided to a timing recovery module. An ADC reconstruction module, based on a first number of pre-cursor estimated bit values, an estimated cursor bit value, and a second number of post-cursor estimated bit values, generates a reconstructed ADC value corresponding to each bit sample. Based on the reconstructed ADC values, the estimated bit values, and the actual ADC values, a corrected bit value is generated for each bit sample.
摘要翻译：描述的实施例从经由通信信道接收的信号恢复定时和数据信息。以通信通道的波特率工作的模数转换器（ADC）产生对应于接收信号的每个位采样的实际ADC值。快速符号估计模块基于实际的ADC值来估计与每个位样本对应的位值。快速符号估计模块以数字时钟速率工作。估计的位值被提供给定时恢复模块。 ADC重建模块基于第一数量的前置光标估计位值，估计光标位值和第二数量的后光标估计位值，产生与每个位样本对应的重构ADC值。基于重建的ADC值，估计位值和实际ADC值，为每个位采样生成一个校正的位值。

12. 发明授权

US09014313B2 Error signature analysis for data and clock recovery in a communication system 有权
标题翻译：通信系统中数据和时钟恢复的错误签名分析
公开(公告)号：US09014313B2
公开(公告)日：2015-04-21
申请号：US13368314
申请日：2012-02-07
申请人： Erik V. Chmelar
发明人： Erik V. Chmelar
IPC分类号： H03D1/04 , H03K5/01 , H04L25/08 , H04L25/03
CPC分类号： H04L25/03057
摘要： Described embodiments recover timing and data information from a signal received via a communication channel. An analog-to-digital converter (ADC) operating at a baud rate of the communication channel generates an actual ADC value corresponding to each bit sample of the received signal. A fast symbol estimation module estimates, based on the actual ADC value, a bit value corresponding to each bit sample. The fast symbol estimation module operates at a digital clock rate. The estimated bit values are provided to a timing recovery module. An ADC reconstruction module, based on a first number of pre-cursor estimated bit values, an estimated cursor bit value, and a second number of post-cursor estimated bit values, generates a reconstructed ADC value corresponding to each bit sample. Based on the reconstructed ADC values, the estimated bit values, and the actual ADC values, a corrected bit value is generated for each bit sample.
摘要翻译：描述的实施例从经由通信信道接收的信号恢复定时和数据信息。以通信通道的波特率工作的模数转换器（ADC）产生对应于接收信号的每个位采样的实际ADC值。快速符号估计模块基于实际的ADC值来估计与每个位样本对应的位值。快速符号估计模块以数字时钟速率工作。估计的位值被提供给定时恢复模块。 ADC重建模块基于第一数量的前置光标估计位值，估计光标位值和第二数量的后光标估计位值，产生与每个位样本对应的重构ADC值。基于重建的ADC值，估计位值和实际ADC值，为每个位采样生成一个校正的位值。

13. 发明授权

US08982941B2 Predictive selection in a fully unrolled decision feedback equalizer 有权
标题翻译：完全展开的决策反馈均衡器中的预测选择
公开(公告)号：US08982941B2
公开(公告)日：2015-03-17
申请号：US13422450
申请日：2012-03-16
申请人： Erik V. Chmelar
发明人： Erik V. Chmelar
IPC分类号： H04L25/03
CPC分类号： H04L25/03057 , H04L25/063 , H04L2025/03496
摘要： Described embodiments provide a non-uniformly quantized analog-to-digital converter (ADC) for generating a value for each sample of a received signal. The ADC includes arrays of decision comparators provided the received signal. Each comparator has a threshold voltage set according to a corresponding bit history of a predictive decision feedback equalizer (DFE), and each bit history is associated with a tap of the DFE. Each comparator provides a bit value based on the corresponding bit history. The predictive DFE includes a set of interleave groups, each interleave group having j interleaves. Each interleave determines a bit value of a corresponding sample in a window of samples. Each tap corresponds to a feedback path between adjacent interleave groups. Multiplexing logic of each interleave predictively selects a bit value of an associated tap based on a value of a corresponding select line in a previous interleave, thereby alleviating a unit interval timing constraint.
摘要翻译：所描述的实施例提供了用于产生接收信号的每个样本的值的非均匀量化的模数转换器（ADC）。 ADC包括提供接收信号的判决比较器阵列。每个比较器具有根据预测判决反馈均衡器（DFE）的相应位历史设置的阈值电压，并且每个位历史与DFE的抽头相关联。每个比较器根据相应的位历史提供一个位值。预测DFE包括一组交织组，每个交织组具有j个交织。每个交错确定样本窗口中相应样本的位值。每个抽头对应于相邻交错组之间的反馈路径。每个交织的复用逻辑基于先前交织中的对应选择行的值来预测性地选择关联抽头的比特值，从而减轻单位间隔时间约束。

14. 发明申请

US20130202065A1 ADAPTATION USING ERROR SIGNATURE ANALYSIS IN A COMMUNICATION SYSTEM 有权
标题翻译：在通信系统中使用错误签名分析的适应
公开(公告)号：US20130202065A1
公开(公告)日：2013-08-08
申请号：US13368315
申请日：2012-02-07
申请人： Erik V. Chmelar
发明人： Erik V. Chmelar
IPC分类号： H04L27/06
CPC分类号： H04L25/03057
摘要： Described embodiments provide method of adapting pulse response taps of a receiver. An analog-to-digital converter (ADC) generates an ADC value for each bit sample of a received signal. An error signature analysis (ESA) module defines a window of bit samples and, for the window, estimates a bit value corresponding to each sample based on the ADC value. The ESA module generates (i) a reconstructed ADC value corresponding to an estimated cursor bit based on a number of pre-cursor estimated bits, the estimated cursor bit, and a number of post-cursor estimated bits, and (ii) an error signature value based on the reconstructed ADC value and the ADC value. Based on the error signature value and a minimum pulse response value, it is determined whether the cursor bit corresponds to residual inter-symbol interference (ISI), and, if so, the error signature value is accumulated and tap values for each pulse response tap are adapted.
摘要翻译：描述的实施例提供了适配接收机的脉冲响应抽头的方法。模数转换器（ADC）为接收信号的每个位采样产生一个ADC值。错误签名分析（ESA）模块定义了位样本窗口，并且对于窗口，基于ADC值估计与每个采样相对应的位值。 ESA模块基于预先估计的比特数，所估计的光标位和一定数量的游标后估计位产生（i）对应于估计的光标位的重建ADC值，以及（ii）错误签名基于重建的ADC值和ADC值。基于错误签名值和最小脉冲响应值，确定光标位是否对应于残余符号间干扰（ISI），如果是，则累积误差签名值，并且每个脉冲响应抽头的抽头值适应。

15. 发明授权

US08432250B2 Process variation based microchip identification 有权
标题翻译：基于工艺变异的微芯片鉴定
公开(公告)号：US08432250B2
公开(公告)日：2013-04-30
申请号：US12059040
申请日：2008-03-31
申请人： Erik V. Chmelar
发明人： Erik V. Chmelar
IPC分类号： G06F7/04
CPC分类号： G06F7/588 , H04L9/0861
摘要： An apparatus comprising a multiplexer circuit, a plurality of bit generation circuits, and a control circuit. The multiplexer circuit may be configured to generate an intermediate signal in response to (i) a plurality of input bits and (ii) a control signal. The plurality of bit generation circuits may each be configured to generate one of the plurality of input bits. The control circuit may be configured to generate the control signal.
摘要翻译：一种装置，包括多路复用器电路，多个位产生电路和控制电路。多路复用器电路可以被配置为响应于（i）多个输入比特和（ii）控制信号而产生中间信号。多个位产生电路可以各自被配置为生成多个输入位之一。控制电路可以被配置为产生控制信号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式