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11. 发明授权

US5543649A Electrostatic discharge protection device for a semiconductor circuit 失效
标题翻译：一种用于半导体电路的静电放电保护装置
公开(公告)号：US5543649A
公开(公告)日：1996-08-06
申请号：US396142
申请日：1995-03-01
申请人： Tae-Han Kim , Sang-Hoon Lee , Dae-Je Chin
发明人： Tae-Han Kim , Sang-Hoon Lee , Dae-Je Chin
IPC分类号： H01L29/78 , H01L27/02 , H01L27/04 , H01L23/62
CPC分类号： H01L27/0266 , H01L27/0259
摘要： The present invention provides an electrostatic discharge protection device of a semiconductor memory device which comprises a gate and a bulk region of first conduction type which are commonly connected to a first power supply, a first diffused region of second conduction type formed in the bulk region, isolated from the gate by a dielectric and connected to the second power supply, and a second diffused region of second conduction type separated from the first diffused region in the bulk region, isolated from the gate by the dielectric and connected to the signal voltage.
摘要翻译：本发明提供一种半导体存储器件的静电放电保护器件，其包括通常连接到第一电源的栅极和主区域，第一导电类型的主体区域，形成在本体区域中的第二导电类型的第一扩散区域，通过电介质隔离并连接到第二电源，以及与主体区域中的第一扩散区分离的第二扩散区域，其通过电介质与栅极隔离并连接到信号电压。

12. 发明授权

US5283760A Data transmission circuit 失效
标题翻译：数据传输电路
公开(公告)号：US5283760A
公开(公告)日：1994-02-01
申请号：US918615
申请日：1992-07-27
申请人： Dae-Je Chin , Byung-Hyuk Min
发明人： Dae-Je Chin , Byung-Hyuk Min
IPC分类号： G11C11/409 , G11C11/4096 , H01L27/10 , G11C7/00
CPC分类号： G11C11/4096
摘要： A data transmission circuit capable of a high-speed data input/output operation and a large-scaled integration for use in a semiconductor memory device, is disclosed. The data transmission circuit has at least one memory cell 51, a word line 52, a pair of bit lines 65, 66, a sense amplifier 55, and a pair of isolation transistors 53, 54. Further, the circuit includes a pair of common input/output lines 67, 68 for transmitting input or output data with a complementary logic operation, a discharging transistor 56 receiving a control signal at its gate and having a channel connected with a ground voltage node, for transferring an electric potential applied to one end of the channel into the ground voltage level, and a pair of transmission transistors 59, 60 receiving the control signal at their respective gates and having each channel connected with the common input/output lines. Two pairs of input transistors 61, 62 and 63, 64 are connected with the bit lines, their channels each being connected between the bit lines 65, 66 and the transmission transistors 59, 60, their gates each connected with the input/output lines. A pair of output transistors 57, 58 each have a gate electrode connected to the bit lines, and having a channel connected between the channel of the discharging transistor 56 and the channel of the transmission transistors 59, 60. To control electrodes of the discharging transistor 56 and the first and second transmission transistor 59, 60 is applied a column selection line (CSL) signal.
摘要翻译：公开了一种能够在半导体存储器件中使用的高速数据输入/输出操作和大规模集成的数据传输电路。数据传输电路具有至少一个存储单元51，字线52，一对位线65,66，读出放大器55和一对隔离晶体管53,54。此外，该电路包括一对公共输入/输出线67,68，用于传输具有互补逻辑操作的输入或输出数据，放电晶体管56在其栅极处接收控制信号，并具有与接地电压节点连接的通道，用于传送施加到一端的电位以及一对发射晶体管59,60，在其各自的栅极处接收控制信号，并且每个通道与公共输入/输出线连接。两对输入晶体管61,62,63,64与位线连接，它们的通道各自连接在位线65,66和透射晶体管59,60之间，它们的栅极各自与输入/输出线连接。一对输出晶体管57,58各自具有连接到位线的栅电极，并且具有连接在放电晶体管56的沟道和透射晶体管59,60的沟道之间的沟道。为了控制放电晶体管的电极 56和第一和第二传输晶体管59,60被施加列选择线（CSL）信号。

13. 发明授权

US5120674A Method of making stacked capacitor DRAM cell 失效
标题翻译：堆叠电容器DRAM单元的制作方法
公开(公告)号：US5120674A
公开(公告)日：1992-06-09
申请号：US431790
申请日：1989-11-06
申请人： Dae-Je Chin , Tae-Young Chung
发明人： Dae-Je Chin , Tae-Young Chung
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10808
摘要： A saddled and wrapped stack capacitor DRAM and a method thereof are provided. The DRAM of the invention includes three foactors in increasing the effective areas for a capacitor. One is a storage poly layer comprising a first poly layer and a second poly layer, which is formed thick in a region over a field oxide layer through two steps; another is a spacer which is formed through an etchback technique for an oxide layer coated on another oxide layer being patterned to selectively remove the storage poly layer, and the spacer makes the storage poly to be remained maximize or be proper by controlling the size thereof; another is an undercut which is formed in boundary regions on an upper oxide layer, on which a plate poly material is coated and wraps.
摘要翻译：提供了一种叠置和堆叠的堆叠电容器DRAM及其方法。本发明的DRAM在增加电容器的有效面积方面包括三个电容。一种是存储多层，其包括第一多晶层和第二多晶硅层，其通过两个步骤在场氧化物层上的区域中形成为厚; 另一个是通过回蚀技术形成的间隔物，其用于涂覆在另一氧化物层上的氧化物层，其被图案化以选择性地除去存储多晶硅层，并且间隔物通过控制其尺寸使储存聚维持最大化或适当; 另一种是形成在上氧化层上的边界区域上的底切，在其上涂覆和包裹平板聚合物材料。

14. 发明授权

US06670950B1 Portable computer and method using an auxilliary LCD panel having a touch screen as a pointing device 有权
标题翻译：使用具有触摸屏的辅助LCD面板作为指示装置的便携式计算机和方法
公开(公告)号：US06670950B1
公开(公告)日：2003-12-30
申请号：US09691241
申请日：2000-10-19
申请人： Dae-Je Chin , Du-Il Kim
发明人： Dae-Je Chin , Du-Il Kim
IPC分类号： G09G500
CPC分类号： G06F1/1692 , G06F1/162 , G06F1/1677 , G06F3/03547 , G06F3/1438 , G09G2330/022 , Y10S345/901 , Y10S345/903
摘要： A portable computer includes a main LCD panel hingedly coupled to a system body, and an auxiliary LCD panel mounted upon the system body. A video image is identically displayed on both the main LCD panel and the auxiliary LCD panel. Alternatively, a definition of the auxiliary LCD panel is lower than that of the main LCD panel. Although a user cannot look at a screen of the main LCD panel, the user can confirm a position of a pointer through a screen of the auxiliary LCD panel. Therefore, the user can precisely control the pointer using a touch screen.
摘要翻译：便携式计算机包括铰链地连接到系统主体的主LCD面板和安装在系统主体上的辅助LCD面板。主要液晶显示面板和辅助液晶显示面板上同时显示视频图像。或者，辅助LCD面板的定义低于主LCD面板的定义。虽然用户不能看到主LCD面板的屏幕，用户可以通过辅助LCD面板的屏幕来确认指针的位置。因此，用户可以使用触摸屏来精确地控制指针。

15. 发明授权

US5430602A Input protection circuit for protecting an internal circuit of a semiconductor device from electrostatic discharge 失效
标题翻译：用于保护半导体器件的内部电路免受静电放电的输入保护电路
公开(公告)号：US5430602A
公开(公告)日：1995-07-04
申请号：US41224
申请日：1993-03-31
申请人： Dae-Je Chin , Jong-Hyeon Choi
发明人： Dae-Je Chin , Jong-Hyeon Choi
IPC分类号： H01L27/06 , H01L27/02 , H02H3/20
CPC分类号： H01L27/0251
摘要： A circuit is provided for protecting the internal circuit of a semiconductor device from electrostatic discharge (ESD). This circuit includes an input pad for applying an input signal to the internal circuit, a metal line for electrically connecting the input pad and internal circuit. This metal line has at least one RC delay stage caused by inherent parasitic resistances and capacitances. Also, a punch-through element is provided to connect the metal line to a ground voltage terminal disposed between the input pad and a delay stage. Finally, a resistor is used to connect the at least one delay stage to the internal circuit.
摘要翻译：提供一种用于保护半导体器件的内部电路免受静电放电（ESD）的电路。该电路包括用于向内部电路施加输入信号的输入焊盘，用于电连接输入焊盘和内部电路的金属线。该金属线具有由固有寄生电阻和电容引起的至少一个RC延迟级。此外，提供穿通元件以将金属线连接到设置在输入焊盘和延迟级之间的接地电压端子。最后，使用电阻器将至少一个延迟级连接到内部电路。

16. 发明授权

US4948993A Distributed sensing control circuit for a sense amplifier of the memory device 失效
标题翻译：用于存储器件的读出放大器的分布式感测控制电路
公开(公告)号：US4948993A
公开(公告)日：1990-08-14
申请号：US290741
申请日：1988-12-27
申请人： Dae-Je Chin , Chang-Hyun Kim , Hong-Sun Hwang
发明人： Dae-Je Chin , Chang-Hyun Kim , Hong-Sun Hwang
IPC分类号： G11C11/409 , G11C7/06 , G11C11/34 , G11C11/401
CPC分类号： G11C7/06
摘要： A distributed control circuit for a sense amplifier is provided in which each sense amplifier has a pair of sensing control transistors connected in serial with each sensing node of the sense amplifiers. Each gate of the sensing control transistors has a respective resistor connected in sequence from the gate of the uppermost sensing control transistor to the gate of the lowermost sensing transistor. A delay compensation resistor is connected by the unit of a sensing control transistor group having the number of the sensing control transistors as many as an integer k.
摘要翻译：提供了一种用于读出放大器的分布式控制电路，其中每个读出放大器具有与感测放大器的每个感测节点串联连接的一对感测控制晶体管。感测控制晶体管的每个栅极具有从最上面的感测控制晶体管的栅极到最下面的感测晶体管的栅极依次连接的相应电阻器。延迟补偿电阻通过感测控制晶体管组的单元连接，其感测控制晶体管的数量多达整数k。

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