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11. 发明申请

US20080170459A1 Memory macro 失效
标题翻译：内存宏
公开(公告)号：US20080170459A1
公开(公告)日：2008-07-17
申请号：US11987536
申请日：2007-11-30
申请人： Motohisa Ikeda
发明人： Motohisa Ikeda
IPC分类号： G11C5/14
CPC分类号： G11C11/413 , G11C5/147 , G11C11/412
摘要： In a memory macro which can more largely reduce a leak current of a memory cell in a hold state, a power voltage between a power potential and a reference potential is supplied across power terminals of each CMOS inverter (across source electrodes of loading P channel FETs and source electrodes of driving N channel FETs) forming the memory cell when a word line is on (high level), a hold enable voltage which is lower than the power voltage and equal to or higher than a lower limit voltage for enabling data to be held (voltage between a potential dropped lower than the power potential and the reference potential) is supplied between the power terminals when the word line is turned off (low level), and the power voltage is constantly supplied to a back gate electrode of one FET within each CMOS inverter.
摘要翻译：在能够更大程度上减小保持状态下的存储单元的泄漏电流的存储器宏中，在每个CMOS反相器的电源端子（跨越加载P沟道FET的源电极）之间提供功率电势和参考电位之间的电源电压和驱动N沟道FET的源电极），当字线为高电平时形成存储单元，保持使能电压低于电源电压并且等于或高于下限电压，以使数据成为当字线关闭（低电平）时，在电源端子之间提供保持（在下降到低于功率电位的电位和参考电位之间的电压），并且电力电压被恒定地提供给一个FET的背栅电极在每个CMOS反相器内。

12. 发明授权

US5502327A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5502327A
公开(公告)日：1996-03-26
申请号：US288035
申请日：1994-08-10
申请人： Motohisa Ikeda
发明人： Motohisa Ikeda
IPC分类号： H01L21/8229 , H01L27/102 , H01L27/02 , H01L29/02
CPC分类号： H01L27/1025 , Y10S257/904
摘要： A semiconductor device includes a first layer made of a first type semiconductor, a second layer provided on the first layer and made of a second type semiconductor, the second layer including low resistance diffusion parts and high resistance diffusion parts, where the first and second type semiconductors are one and the other of n-type and p-type semiconductors, a third layer provided on the low resistance diffusion parts of the second layer and made of the first semiconductor type, thereby forming a pair of transistors which form a flip-flop and use the high resistance diffusion parts as balanced load resistors, and at least first and second isolations isolating the flip-flop. Each of the high resistance diffusion parts of the second layer comprise a first linear part separated by a predetermined distance from the first isolation, a second linear part separated by the predetermined distance from the second isolation and having a width identical to that of the first linear part, and a third linear part connecting the first and second linear parts.
摘要翻译：半导体器件包括由第一类型半导体制成的第一层，设置在第一层上并由第二类型半导体制成的第二层，第二层包括低电阻扩散部分和高电阻扩散部分，其中第一和第二类型半导体是n型和p型半导体中的另一种，第三层设置在第二层的低电阻扩散部分上并由第一半导体类型制成，从而形成一对形成触发器的晶体管并且使用高电阻扩散部件作为平衡负载电阻器，以及至少隔离触发器的第一和第二隔离器。第二层的高电阻扩散部分中的每一个包括与第一隔离部隔开预定距离的第一线性部分，与第二隔离部隔开预定距离的第二直线部分，并且具有与第一线性部分相同的宽度部分和连接第一和第二直线部分的第三直线部分。

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