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11. 发明申请

US20180285106A1 HIERARCHICAL GENERAL REGISTER FILE (GRF) FOR EXECUTION BLOCK 审中-公开
公开(公告)号：US20180285106A1
公开(公告)日：2018-10-04
申请号：US15477033
申请日：2017-04-01
申请人： Abhishek R. Appu , Altug Koker , Joydeep Ray , Kamal Sinha , Kiran C. Veernapu , Subramaniam Maiyuran , Prasoonkumar Surti , Guei-Yuan Lueh , David Puffer , Supratim Pal , Eric J. Hoekstra , Travis T. Schluessler , Linda L. Hurd
发明人： Abhishek R. Appu , Altug Koker , Joydeep Ray , Kamal Sinha , Kiran C. Veernapu , Subramaniam Maiyuran , Prasoonkumar Surti , Guei-Yuan Lueh , David Puffer , Supratim Pal , Eric J. Hoekstra , Travis T. Schluessler , Linda L. Hurd
IPC分类号： G06F9/30 , G06T15/00 , G06T1/60 , G06T1/20 , G06F9/46 , G09G5/36
摘要： In an example, an apparatus comprises a plurality of execution units, and a first general register file (GRF) communicatively couple to the plurality of execution units, wherein the first GRF is shared by the plurality of execution units. Other embodiments are also disclosed and claimed.

12. 发明授权

US09612835B2 MFENCE and LFENCE micro-architectural implementation method and system 有权
公开(公告)号：US09612835B2
公开(公告)日：2017-04-04
申请号：US13619919
申请日：2012-09-14
申请人： Salvador Palanca , Stephen A. Fischer , Subramaniam Maiyuran , Shekoufeh Qawami
发明人： Salvador Palanca , Stephen A. Fischer , Subramaniam Maiyuran , Shekoufeh Qawami
IPC分类号： G06F15/00 , G06F9/30 , G06F9/40 , G06F9/38
CPC分类号： G06F9/3836 , G06F9/30043 , G06F9/30047 , G06F9/30087 , G06F9/3012 , G06F9/30145 , G06F9/3808 , G06F9/3812 , G06F9/3834 , G06F9/3855 , G06F9/3857 , G06F9/3867 , G06F2009/45583 , G06F2009/45591
摘要： A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.

13. 发明申请

US20120198208A1 SHARED FUNCTION MULTI-PORTED ROM APPARATUS AND METHOD 有权
标题翻译：共享功能多点ROM设备和方法
公开(公告)号：US20120198208A1
公开(公告)日：2012-08-02
申请号：US13338887
申请日：2011-12-28
申请人： Satish K. Damaraju , Subramaniam Maiyuran
发明人： Satish K. Damaraju , Subramaniam Maiyuran
IPC分类号： G06F9/30
CPC分类号： G06F9/3877 , G06F7/544 , G06F9/3001 , G06F9/30036
摘要： Various embodiments may be disclosed that may share a ROM pull down logic circuit among multiple ports of a processing core. The processing core may include an execution unit (EU) having an array of read only memory (ROM) pull down logic storing math functions. The ROM pull down logic circuit may implement single instruction, multiple data (SIMD) operations. The ROM pull down logic circuit may be operatively coupled with each of the multiple ports in a multi-port function sharing arrangement. Sharing the ROM pull down logic circuit reduces the need to duplicate logic and may result in a savings of chip area as well as a savings of power.
摘要翻译：可以公开可以在处理核心的多个端口中共享ROM下拉逻辑电路的各种实施例。处理核心可以包括具有存储数学函数的只读存储器（ROM）下拉逻辑阵列的执行单元（EU）。 ROM下拉逻辑电路可以实现单指令，多数据（SIMD）操作。 ROM下拉逻辑电路可以在多端口功能共享装置中与多个端口中的每一个可操作地耦合。共享ROM下拉逻辑电路减少了重复逻辑的需要，并且可以节省芯片面积以及节省功率。

14. 发明授权

US06665775B1 Cache dynamically configured for simultaneous accesses by multiple computing engines 有权
标题翻译：缓存动态配置为同时访问多个计算引擎
公开(公告)号：US06665775B1
公开(公告)日：2003-12-16
申请号：US09667688
申请日：2000-09-22
申请人： Subramaniam Maiyuran , Salvador Palanca
发明人： Subramaniam Maiyuran , Salvador Palanca
IPC分类号： G06F1208
CPC分类号： G06F12/0848 , G06F12/084 , G06F12/0846
摘要： A cache has an array with single ported cells and is dynamically accessible simultaneously by multiple computing engines. In a further embodiment, the cache also has a tag array including a first address input, a second address input, and a shared mode input, and a data array electrically coupled to the tag array and including a first address input, a second address input, and a shared mode input.
摘要翻译：缓存具有单个移植单元的阵列，并且可由多个计算引擎同时动态访问。在另一实施例中，高速缓存还具有包括第一地址输入，第二地址输入和共享模式输入的标签阵列，以及电耦合到标签阵列的数据阵列，并且包括第一地址输入，第二地址输入，和共享模式输入。

15. 发明授权

US06604162B1 Snoop stall reduction on a microprocessor external bus 有权
标题翻译：微处理器外部总线上的监听减速
公开(公告)号：US06604162B1
公开(公告)日：2003-08-05
申请号：US09606837
申请日：2000-06-28
申请人： Lokpraveen B. Mosur , Subramaniam Maiyuran
发明人： Lokpraveen B. Mosur , Subramaniam Maiyuran
IPC分类号： G06F1342
CPC分类号： G06F12/0831 , G06F13/4243
摘要： A method and apparatus for reducing snoop stall on an external bus. One method of the present invention comprises retrieving an address and a transaction attribute for a bus transaction during a first of a plurality of request phase packets of the bus transaction. Then it is determined whether the bus transaction is a snoopable memory transaction or not. If the bus transaction is a snoopable memory transaction, a snoop probe is dispatched during the first request phase packet of the transaction. Snooping devices are allowed additional bus clocks to respond to the snoop probe, thereby reducing the number of snoop stalls required to be inserted during the bus transaction.
摘要翻译：一种用于减少外部总线上的窥探失速的方法和装置。本发明的一种方法包括在总线事务的多个请求阶段分组的第一个期间检索总线事务的地址和事务属性。然后确定总线事务是否是可窥探的存储器事务。如果总线事务是可窥探的内存事务，则在事务的第一请求阶段数据包期间调度侦听器探测。侦听设备允许额外的总线时钟响应窥探探针，从而减少在总线事务期间插入所需的监听档位数。

16. 发明授权

US06507219B2 Charge sharing and charge recycling for an on-chip bus 失效
公开(公告)号：US06507219B2
公开(公告)日：2003-01-14
申请号：US09962716
申请日：2001-09-21
申请人： Sanjay Dabral , Ming Zeng , Subramaniam Maiyuran
发明人： Sanjay Dabral , Ming Zeng , Subramaniam Maiyuran
IPC分类号： H03K19094
CPC分类号： G11C7/106 , G06F13/4077 , G11C7/1051 , G11C7/1078 , G11C7/1087 , H03K19/01855 , Y02D10/14 , Y02D10/151
摘要： A method for charge sharing among data conductors of a bus. The bus has a first data conductor and a corresponding data conductor. The method includes detecting the logic levels on the first data conductor and the corresponding data conductor, and generating a charge sharing signal for sharing charge between the first data conductor and the corresponding data conductor.

17. 发明授权

US06356270B2 Efficient utilization of write-combining buffers 失效
标题翻译：高效利用写入组合缓冲区
公开(公告)号：US06356270B2
公开(公告)日：2002-03-12
申请号：US09053231
申请日：1998-03-31
申请人： Vladimir Pentkovski , Hsien-Cheng E. Hsieh , Hsien-Hsin Lee , Subramaniam Maiyuran
发明人： Vladimir Pentkovski , Hsien-Cheng E. Hsieh , Hsien-Hsin Lee , Subramaniam Maiyuran
IPC分类号： G06T160
CPC分类号： G06F9/30043 , G06F9/3824 , G06F12/0875
摘要： The present invention discloses a method and apparatus method for efficient utilization of write-combining buffers for a sequence of non-temporal stores to scattered locations. The method comprises: converting the sequence of non-temporal stores to stores to intermediate buffers; and grouping the stores to intermediate buffers into consecutive non-temporal stores. The consecutive non-temporal stores correspond to adjacent memory locations in the write-combining buffers.
摘要翻译：本发明公开了一种用于对分散位置的非时间存储序列的写合成缓冲器有效利用的方法和装置方法。该方法包括：将非时间存储序列转换为存储到中间缓冲器; 并将商店分组到中间缓冲器到连续的非时间商店。连续的非时间存储对应于写合成缓冲器中的相邻存储器位置。

18. 发明授权

US10649956B2 Engine to enable high speed context switching via on-die storage 有权
公开(公告)号：US10649956B2
公开(公告)日：2020-05-12
申请号：US15477027
申请日：2017-04-01
申请人： Altug Koker , Prasoonkumar Surti , David Puffer , Subramaniam Maiyuran , Guei-Yuan Lueh , Abhishek R. Appu , Joydeep Ray , Balaji Vembu , Tomer Bar-On , Andrew T. Lauritzen , Hugues Labbe , John G. Gierach , Gabor Liktor
发明人： Altug Koker , Prasoonkumar Surti , David Puffer , Subramaniam Maiyuran , Guei-Yuan Lueh , Abhishek R. Appu , Joydeep Ray , Balaji Vembu , Tomer Bar-On , Andrew T. Lauritzen , Hugues Labbe , John G. Gierach , Gabor Liktor
IPC分类号： G06F16/13 , G06F9/38 , G06F9/30 , G06F16/11 , G06F16/172 , G06F9/46 , G06F12/1036 , G06F12/1045 , G06F12/0831
摘要： In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.

19. 发明申请

US20180300238A1 ADAPTIVE CACHE SIZING PER WORKLOAD 审中-公开
公开(公告)号：US20180300238A1
公开(公告)日：2018-10-18
申请号：US15488637
申请日：2017-04-17
申请人： Balaji Vembu , Altug Koker , Josh B. Mastronarde , Nikos Kaburlasos , Abhishek R. Appu , Sanjeev S. Jahagirdar , Eric J. Asperheim , Subramaniam Maiyuran , Kiran C. Veernapu , Pattabhiraman K , Kamal Sinha , Bhushan M. Borole , Wenyin Fu , Joydeep Ray , Prasoonkumar Surti , Eric J. Hoekstra , Travis T. Schluessler , Linda L. Hurd
发明人： Balaji Vembu , Altug Koker , Josh B. Mastronarde , Nikos Kaburlasos , Abhishek R. Appu , Sanjeev S. Jahagirdar , Eric J. Asperheim , Subramaniam Maiyuran , Kiran C. Veernapu , Pattabhiraman K , Kamal Sinha , Bhushan M. Borole , Wenyin Fu , Joydeep Ray , Prasoonkumar Surti , Eric J. Hoekstra , Travis T. Schluessler , Linda L. Hurd
IPC分类号： G06F12/06
摘要： Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to monitor cache utilization of an application during execution of the application for a workload; and a memory to store cache utilization statistics responsive to the monitored cache utilization. The processor is to determine an optimal cache configuration for the application based at least in part on the cache utilization statistics for the workload such that a smallest amount of cache is turned on for subsequent executions of the workload by the application.

20. 发明申请

US20180096446A1 Graphics Processor Register Renaming Mechanism 审中-公开
公开(公告)号：US20180096446A1
公开(公告)日：2018-04-05
申请号：US15281276
申请日：2016-09-30
申请人： Kaiyu Chen , Guei-Yuan Lueh , Subramaniam Maiyuran
发明人： Kaiyu Chen , Guei-Yuan Lueh , Subramaniam Maiyuran
IPC分类号： G06T1/20 , G06T1/60 , G06T15/00 , G06T15/80
摘要： A processing apparatus is described. The apparatus includes a graphics processing unit (GPU), including a plurality of execution units to process graphics context data and a register file having a plurality of registers to store the graphics context data; and register renaming logic to facilitate dynamic renaming of the plurality of registers by logically partitioning the plurality of registers in the register file into a set of fixed registers and a set of shared registers.

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