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11. 发明授权

US6014763A At-speed scan testing 失效
标题翻译：高速扫描测试
公开(公告)号：US6014763A
公开(公告)日：2000-01-11
申请号：US7670
申请日：1998-01-15
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Kevin John Nowka , Joel Abraham Silberman
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Kevin John Nowka , Joel Abraham Silberman
IPC分类号： G01R31/28
CPC分类号： G01R31/318572
摘要： A method of scanning an integrated circuit, by converting a parallel scan input (scan data and scan control) to serial, passing the serial scan input through scan circuitry to create a serial scan output, converting the scan output from serial to parallel, transmitting the scan output in parallel from the integrated circuit to the tester. A tester clock signal is derived by synchronizing the tester to a divided clock signal (1/N) of the integrated circuit. Communications take place at a speed of the tester clock signal, but the scan operates at the full operational speed of the device under test. At-speed scan testing can be achieved for speeds in excess of 1 GHz.
摘要翻译：通过将并行扫描输入（扫描数据和扫描控制）转换为串行扫描来扫描集成电路的方法，将串行扫描输入通过扫描电路传送以创建串行扫描输出，将扫描输出从串行转换为并行转换，从集成电路并行扫描输出到测试仪。通过将测试仪与集成电路的分频时钟信号（1 / N）同步，得到测试仪时钟信号。通信以测试仪时钟信号的速度进行，但扫描以被测设备的全部操作速度运行。对于超过1 GHz的速度，可以实现高速扫描测试。

12. 发明授权

US06772368B2 Multiprocessor with pair-wise high reliability mode, and method therefore 失效
标题翻译：具有成对的高可靠性模式的多处理器和方法
公开(公告)号：US06772368B2
公开(公告)日：2004-08-03
申请号：US09734117
申请日：2000-12-11
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Ravi Nair , Steven Douglas Posluszny
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Ravi Nair , Steven Douglas Posluszny
IPC分类号： G06F1116
CPC分类号： G06F11/1641 , G06F9/30189 , G06F9/3861 , G06F9/3885 , G06F11/1407 , G06F2201/845
摘要： In one embodiment a multiprocessing apparatus includes a first processor and a second processor. Each of the processors have their own data and instruction caches to support independent operation. In a normal mode the processors independently execute separate instruction streams. Each of the processors has a respective signature generator. The system also includes a compare unit coupled to the signature generators. In a high reliability mode, both processors execute the same instruction stream. That is, each processor computes a version of a result for ones of the instructions in the stream. Responsive to the respective versions, the respective signature generators assert signatures to the compare unit, so that a faulting instruction may be detected. In another aspect, each processor has its own respective commit logic. The compare unit signals the commit logic in each respective processor that the possibility has been eliminated of a calculation interrupt arising for that instruction, once the compare unit receives signatures for corresponding versions of a result, but only if the signatures match. This permits the commit logic to commit the result. If the signatures do not match, the compare unit signals the commit logic that the corresponding instruction has faulted. The commit logic permits instructions prior to the faulting instruction in program order to continue execution, but initiates flushing of results that were produced by the faulting instruction and at least some instructions subsequent in program order to the faulting instruction.
摘要翻译：在一个实施例中，多处理装置包括第一处理器和第二处理器。每个处理器都有自己的数据和指令高速缓存来支持独立操作。在正常模式下，处理器独立地执行单独的指令流。每个处理器具有相应的签名生成器。该系统还包括耦合到签名生成器的比较单元。在高可靠性模式下，两个处理器执行相同的指令流。也就是说，每个处理器计算流中的指令的结果的版本。响应于各自的版本，相应的签名生成器向比较单元提供签名，从而可以检测到故障指令。在另一方面，每个处理器具有其各自的提交逻辑。一旦比较单元接收到相应版本的结果的签名，但只有当签名匹配时，比较单元才会发信号通知每个相应处理器中的提交逻辑已经消除了该指令产生的计算中断的可能性。这允许提交逻辑提交结果。如果签名不匹配，则比较单元向提交逻辑发出相应指令发生故障的信号。提交逻辑允许以程序顺序执行故障指令之前的指令继续执行，但是启动由故障指令产生的结果和程序顺序中的至少一些指令冲洗到故障指令。

13. 发明授权

US06760819B2 Symmetric multiprocessor coherence mechanism 有权
标题翻译：对称多处理器一致性机制
公开(公告)号：US06760819B2
公开(公告)日：2004-07-06
申请号：US09895888
申请日：2001-06-29
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Charles Ray Johns , John Samuel Liberty , Thuong Quang Truong
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Charles Ray Johns , John Samuel Liberty , Thuong Quang Truong
IPC分类号： G06F1208
CPC分类号： G06F12/0822 , G06F12/0811 , G06F12/084
摘要： A processor-cache operational scheme and topology within a multi-processor data processing system having a shared lower level cache (or memory) by which the number of coherency busses is reduced and more efficient snoop resolution and coherency operations with the processor caches are provided. A copy of the internal (L1) cache directory is provided within the lower level (L2) cache or memory. The snoop operations and coherency maintenance operations of the L1 directory are completed by comparing the snoop addresses with the address tags of the copy of the L1 directory in the L2 cache. Updates to the coherency states of the copy of the L1 directory are mirrored in the L1 directory and L1 cache. This eliminates the need for the individual coherency buses of each processor that is coupled to the L2 cache and speeds up coherency operations because the snoops do not have to be transmitted to the L1 caches.
摘要翻译：提供具有共享低级高速缓存（或存储器）的多处理器数据处理系统中的处理器 - 高速缓存操作方案和拓扑，通过该共享低级高速缓存（或存储器）减少一致性总线的数量并且提供与处理器高速缓存更有效的窥探分辨率和一致性操作。在低级（L2）高速缓存或内存中提供内部（L1）缓存目录的副本。通过将侦听地址与L2缓存中L1目录的副本的地址标签进行比较，完成L1目录的侦听操作和一致性维护操作。对L1目录的副本的一致性状态的更新被镜像在L1目录和L1缓存中。这消除了对耦合到L2高速缓存的每个处理器的各个一致性总线的需要，并且加速一致性操作，因为该探测不必被传送到L1高速缓存。

14. 发明授权

US06983387B2 Microprocessor chip simultaneous switching current reduction method and apparatus 有权
标题翻译：微处理器芯片同时开关电流降低方法和装置
公开(公告)号：US06983387B2
公开(公告)日：2006-01-03
申请号：US10273617
申请日：2002-10-17
申请人： David William Boerstler , Sang Hoo Dhong , Harm Peter Hofstee , Peichun Peter Liu
发明人： David William Boerstler , Sang Hoo Dhong , Harm Peter Hofstee , Peichun Peter Liu
IPC分类号： H03L7/06
CPC分类号： G06F1/06 , G06F1/10
摘要： Disclosed is an electronic chip containing a plurality of electronic circuit partitions, distributed over the area of the chip, each including a processor core and a clock phase domain different from cores in other partitions of the chip. A source of same frequency, but different phase clock signals representing different clock domains, provides different phase signals to adjacent partitions for the purpose of reducing instantaneous magnitude switching currents. Intra-chip communication circuitry distributes control and data signals between partitions.
摘要翻译：公开了一种电子芯片，其包含分布在芯片的区域上的多个电子电路分区，每个电子部件分别包括处理器核心和与芯片的其他分区中的核心不同的时钟相位域。相同频率的源，但是表示不同时钟域的不同相位时钟信号，为了减小瞬时幅度切换电流，向相邻分区提供不同的相位信号。片内通信电路在分区之间分配控制和数据信号。

15. 发明授权

US06982954B2 Communications bus with redundant signal paths and method for compensating for signal path errors in a communications bus 失效
标题翻译：具有冗余信号路径的通信总线和用于补偿通信总线中的信号路径错误的方法
公开(公告)号：US06982954B2
公开(公告)日：2006-01-03
申请号：US09848175
申请日：2001-05-03
申请人： Sang Hoo Dhong , Harm Peter Hofstee
发明人： Sang Hoo Dhong , Harm Peter Hofstee
IPC分类号： G01R31/08
CPC分类号： G06F11/2007
摘要： A communications bus (300) includes a number of alternate transmission paths (311, 312) between a given source node (301) and respective destination node (305) on a common substrate. The source node (301) receives a signal from a first circuit (309) serviced by the bus (300) while the respective destination node (305) transfers that signal to a second circuit (310) serviced by the bus. The communications bus (300) includes two switching arrangements for switching between the alternate transmission paths (311, 312). A source switching arrangement (318) is interposed between the source node (301) and the respective alternate transmission path (311, 312). This source switching arrangement (318) selectively connects the respective source node (301) to a selected one of the alternate transmission paths (311, 312) and disconnects the source node (301) from each other alternate transmission path. A destination switching arrangement (319) is interposed between the destination node (305) and respective alternate transmission paths (311, 312). The destination switching arrangement (319) selectively connects the respective destination node (305) to the selected alternate transmission path and disconnects the respective destination node from each other alternate transmission path.
摘要翻译：通信总线（300）包括在公共基板上的给定源节点（301）和相应目的地节点（305）之间的多个替代传输路径（311,312）。源节点（301）从由总线（300）服务的第一电路（309）接收信号，而各个目的地节点（305）将该信号传送到由总线服务的第二电路（310）。通信总线（300）包括用于在备选传输路径（311,312）之间切换的两个切换装置。源切换装置（318）插入在源节点（301）和相应的备选传输路径（311,312）之间。该源切换装置（318）选择性地将相应的源节点（301）连接到所选择的一个备选传输路径（311,312），并且将源节点（301）与彼此的替代传输路径断开连接。目的地交换装置（319）介于目的地节点（305）和相应的备选传输路径（311,312）之间。目的地交换装置（319）选择性地将各目的地节点（305）连接到所选择的备选传输路径，并且将相应的目的地节点与彼此的备选传输路径断开连接。

16. 发明授权

US06915506B2 Method and apparatus for evaluating results of multiple software tools 失效
标题翻译：用于评估多种软件工具的结果的方法和装置
公开(公告)号：US06915506B2
公开(公告)日：2005-07-05
申请号：US09817138
申请日：2001-03-27
申请人： Sang Hoo Dhong , Sam Dinkin , Harm Peter Hofstee , Stephen Douglas Posluszny
发明人： Sang Hoo Dhong , Sam Dinkin , Harm Peter Hofstee , Stephen Douglas Posluszny
IPC分类号： G06F17/50 , G06F9/44
CPC分类号： G06F17/50
摘要： A method and structure for optimizing a solution for a complex problem typically solved by software tools includes selectively converting problem data into a format appropriate for one or more preselected vendor's set of solution tools and inputting the formatted design data into the one or more preselected vendor's set of solution tools. If more than one vendor has been preselected, resultant solution results are compared and the optimum solution is selected.
摘要翻译：用于优化通常由软件工具解决的复杂问题的解决方案的方法和结构包括将问题数据选择性地转换成适合于一个或多个预选供应商的解决方案工具集合的格式，并将格式化的设计数据输入到一个或多个预先选择的供应商集合的解决方案工具。如果预先选择了多个供应商，则比较所得到的解决方案结果并选择最佳解决方案。

17. 发明授权

US06717882B1 Cell circuit for multiport memory using 3-way multiplexer 失效
标题翻译：使用3路复用器的多端口存储器的单元电路
公开(公告)号：US06717882B1
公开(公告)日：2004-04-06
申请号：US10273590
申请日：2002-10-17
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Shoji Onishi , Osamu Takahashi
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Shoji Onishi , Osamu Takahashi
IPC分类号： G11C800
CPC分类号： G11C8/16
摘要： An improved cell circuit for data readout for use in a multiport memory is provided. The multiport memory stores write data signals. The cell circuit includes a plurality of multiplexers each coupled to a discharge device. Each of the multiplexers receives a subset of the write data signals and a plurality of read wordline signals and selects an output enable signal among the subset of the write data signals based on the read wordline signals. Each of the discharge devices are coupled to one of the multiplexers for receiving the output enable signal to generate a drive signal for driving one or more bitlines of the multiport memory.
摘要翻译：提供用于多端口存储器中的用于数据读出的改进的单元电路。多端口存储器存储写入数据信号。电池电路包括多个多路复用器，每个多路复用器耦合到放电装置。每个多路复用器接收写入数据信号的子集和多个读取字线信号，并且基于所读取的字线信号在写入数据信号的子集中选择输出使能信号。每个放电装置耦合到多路复用器中的一个，用于接收输出使能信号，以产生用于驱动多端口存储器的一个或多个位线的驱动信号。

18. 发明授权

US07447725B2 Apparatus for controlling rounding modes in single instruction multiple data (SIMD) floating-point units 失效
标题翻译：用于在单指令多数据（SIMD）浮点单元中控制舍入模式的装置
公开(公告)号：US07447725B2
公开(公告)日：2008-11-04
申请号：US10982110
申请日：2004-11-05
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Christian Jacobi , Silvia Melitta Mueller , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Christian Jacobi , Silvia Melitta Mueller , Hwa-Joon Oh
IPC分类号： G06F7/38
CPC分类号： G06F7/49947 , G06F7/483 , G06F7/49968 , G06F7/49973 , G06F7/49989 , G06F2207/3828
摘要： An apparatus for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control register (FPSCR) having a first rounding mode bit field and a second rounding mode bit field. The SIMD floating-point unit also includes means for generating a first slice and a second slice. During a floating-point operation, the SIMD floating-point unit concurrently performs a first rounding operation on the first slice and a second rounding operation on the second slice according to a bit in the first rounding mode bit field and a bit in the second rounding mode bit field within the FPSCR, respectively.
摘要翻译：公开了一种用于在单指令多数据（SIMD）浮点单元中控制舍入模式的装置。 SIMD浮点单元包括具有第一舍入模式位字段和第二舍入模式位字段的浮点状态和控制寄存器（FPSCR）。 SIMD浮点单元还包括用于生成第一切片和第二切片的装置。在浮点运算期间，SIMD浮点单元根据第一舍入模式位字段中的位并且在第二舍入中的位同时对第一切片进行第一舍入运算，并对第二切片进行第二舍入运算 FPSCR中的模式位字段。

19. 发明授权

US07406589B2 Processor having efficient function estimate instructions 失效
标题翻译：处理器具有有效的功能估计指令
公开(公告)号：US07406589B2
公开(公告)日：2008-07-29
申请号：US11127848
申请日：2005-05-12
申请人： Sang Hoo Dhong , Gordon Clyde Fossum , Harm Peter Hofstee , Brad William Michael , Silvia Melitta Mueller , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Gordon Clyde Fossum , Harm Peter Hofstee , Brad William Michael , Silvia Melitta Mueller , Hwa-Joon Oh
IPC分类号： G06F7/552 , G06F7/544 , G06F7/38
CPC分类号： G06F7/483 , G06F7/535 , G06F7/5443 , G06F7/5525 , G06F9/30014 , G06F2207/5356
摘要： High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instruction is provided for each different function, while only a single interpolation instruction is needed, since the single interpolation instruction can perform the interpolation step for any of the functions to be estimated. Thus, significantly less overhead is incurred than would be incurred with specialized hardware, while still maintaining a uniform FPU latency, which allows for much simpler control logic.
摘要翻译：高精度浮点函数估计分为两个指令：低精度表查找指令和线性插值指令。可以使用该方案来实现不同功能的估计：为每个不同的功能提供单独的表查找指令，而仅需要单个插补指令，因为单个内插指令可以执行任何功能的内插步骤估计。因此，与专用硬件相比，产生的开销大大降低，同时仍保持统一的FPU延迟，这允许更简单的控制逻辑。

20. 发明授权

US06268660B1 Silicon packaging with through wafer interconnects 有权
标题翻译：通过晶圆互连的硅封装
公开(公告)号：US06268660B1
公开(公告)日：2001-07-31
申请号：US09263032
申请日：1999-03-05
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Michael Jay Shapiro
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Michael Jay Shapiro
IPC分类号： H01L2348
CPC分类号： H01L23/5384 , H01L23/481 , H01L2224/16 , H01L2924/01322 , H01L2924/10253 , H01L2924/00
摘要： A package for integrated circuit chips. The package contains a silicon substrate having a top surface and a bottom surface. The package also contains a first means for electrically connecting the integrated circuits to the substrate attached to the top surface of the substrate. A multilevel wiring is located at the top surface and is coupled to the first connecting means and serves as a communication link among a plurality of the first connecting means to enable multi-chip processing. A via containing means for coupling the multilevel wiring at the top surface to the bottom surface runs through the substrate from the bottom surface to the top surface. A second means is also present for connecting the coupling means at the bottom surface of the substrate with external components.
摘要翻译：集成电路芯片封装。该封装包含具有顶表面和底表面的硅衬底。封装还包含用于将集成电路电连接到附接到衬底顶表面的衬底的第一装置。多层布线位于顶表面并且耦合到第一连接装置，并且用作多个第一连接装置之间的通信链路，以实现多芯片处理。用于将上表面的多层布线耦合到底表面的通孔容纳装置从底表面到顶表面穿过基底。还存在用于将基板的底表面处的耦合装置与外部部件连接的第二装置。

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