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11. 发明申请

US20150311189A1 LOW NOISE AND HIGH PERFORMANCE LSI DEVICE 审中-公开
标题翻译：低噪声和高性能LSI器件
公开(公告)号：US20150311189A1
公开(公告)日：2015-10-29
申请号：US14791770
申请日：2015-07-06
申请人： Samsung Electronics Co., Ltd.
发明人： Shigenobu Maeda , Jeong-Hwan Yang
IPC分类号： H01L27/02 , H01L27/092 , H01L29/78
CPC分类号： H01L27/0922 , H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L27/0207 , H01L27/092 , H01L27/1052 , H01L29/0649 , H01L29/665 , H01L29/7833 , H01L29/7842 , H01L29/7843 , H01L29/7845 , H01L29/7848
摘要： In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate. For example, mechanical stress can be applied to devices that operate in high-speed digital settings, while devices that operate in analog or RF signal settings, in which electrical noise such as flicker noise that may be introduced by applied stress may degrade performance, have no stress applied.
摘要翻译：在其中使用NMOS器件和PMOS器件的半导体器件中，以不同的模式（例如模拟和数字模式）来执行应力工程，根据所需的操作模式，对特定器件有选择地施加应力工程。也就是说，适当的机械应力，即拉伸或压缩，可以施加到和/或从设备（即，NMOS和/或PMOS器件）中去除和/或从器件去除，不仅基于它们的导电类型，即n型或p- 类型，而且还在于其预期的操作应用，例如模拟/数字，低电压/高电压，高速/低速，噪声敏感/噪声不敏感等。结果是个体的性能设备根据其运行模式进行优化。例如，机械应力可以应用于在高速数字设置中工作的设备，而在模拟或RF信号设置中工作的设备，其中可能由施加的应力引入的诸如闪烁噪声的电噪声可能降低性能，具有没有施加应力。

12. 发明授权

US09087842B2 Semiconductor device including fuse structure 有权
标题翻译：半导体器件包括熔丝结构
公开(公告)号：US09087842B2
公开(公告)日：2015-07-21
申请号：US14304750
申请日：2014-06-13
申请人： Samsung Electronics Co., Ltd.
发明人： Hyun-Min Choi , Shigenobu Maeda , Ji-Hoon Yoon , Sung-Man Lim
IPC分类号： H01L27/10 , H01L29/00 , H01L23/525 , H01L23/522
CPC分类号： H01L23/5256 , H01L21/76807 , H01L21/76843 , H01L21/76865 , H01L23/5226 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a substrate having a fuse area and a device area; a fuse structure in an insulating layer of the fuse area, and a wire structure in the insulating layer of the device area. The fuse structure includes a fuse via, a fuse line electrically connected to a top end of the fuse via pattern and extending in a direction. The wire structure includes a wire via, a wire line electrically connected to a top end of the wire via and extending in the first direction. A width in the first direction of the fuse via is smaller than a width in the first direction of the wire via.
摘要翻译：半导体器件包括具有熔丝区域和器件区域的衬底; 保险丝区域的绝缘层中的熔丝结构，以及设备区域的绝缘层中的线结构。熔丝结构包括熔丝通孔，熔丝线与熔丝通孔图案的顶端电连接并沿一个方向延伸。导线结构包括导线通孔，电线连接到导线通孔的顶端并沿第一方向延伸的导线。保险丝通孔的第一方向上的宽度小于电线通路的第一方向上的宽度。

13. 发明公开

US20240178068A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING A FIN-TYPE ACTIVE REGION 审中-公开
公开(公告)号：US20240178068A1
公开(公告)日：2024-05-30
申请号：US18383940
申请日：2023-10-26
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Seungju HWANG , Shigenobu Maeda , Myoungkyu PARK
IPC分类号： H01L21/8234 , H01L21/762 , H01L27/088
CPC分类号： H01L21/823431 , H01L21/76224 , H01L21/823481 , H01L27/0886
摘要： A method of manufacturing a semiconductor device includes: forming a plurality of first mandrel patterns at a first mandrel pitch on a substrate; forming a first fin group and a first dummy fin group by patterning the substrate, wherein the first fin group is adjacent to the first dummy fin group in a first direction; and removing the first dummy fin group, wherein the first fin group includes a first fin and a second fin adjacent to each other and arranged at a first fin pitch in the first direction. The first dummy fin group includes a first dummy fin and a second dummy fin adjacent to each other and arranged at the first fin pitch in the first direction. The second fin and the first dummy fin, which is adjacent to the second fin, are arranged at a second fin pitch that is greater than the first fin pitch.

14. 发明授权

US10749000B2 Field effect transistor with channel layer, and semiconductor device including the same 有权
公开(公告)号：US10749000B2
公开(公告)日：2020-08-18
申请号：US15911182
申请日：2018-03-05
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Shigenobu Maeda , Seunghan Seo , Yeohyun Sung
IPC分类号： H01L29/06 , H01L29/16 , H01L29/165 , H01L29/267 , H01L29/778 , H01L29/786 , H01L29/24 , H01L29/66 , H01L29/04 , H01L29/08 , H01L29/10 , H01L29/20 , H01L29/22 , H01L29/78 , H01L29/51
摘要： A semiconductor device, a field effect transistor, and a fin field effect transistor are provided. The semiconductor device may include a channel layer, a source/drain layer, and a gate electrode. The channel layer is provided on a substrate and extends in a direction perpendicular to a top surface of the substrate. The source/drain layer is disposed at a side of the channel layer and is electrically connected to the channel layer. The gate electrode is provided adjacent to at least one of surfaces of the channel layer. The channel layer includes a two-dimensional atomic layer made of a first material.

15. 发明授权

US09627314B2 Fuse structure and method of blowing the same 有权
公开(公告)号：US09627314B2
公开(公告)日：2017-04-18
申请号：US14986872
申请日：2016-01-04
申请人： Samsung Electronics Co., Ltd.
发明人： Hyun-Min Choi , Shigenobu Maeda
IPC分类号： H01L23/525 , H01L23/62 , H01L21/768 , H01L23/498 , H01L23/522 , H01L23/528 , H01L23/532 , H01L27/112
CPC分类号： H01L23/5256 , H01L21/76886 , H01L23/49827 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L23/62 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure and a method of blowing the same are provided. The fuse structure includes a conductive line on a substrate, first and second vias on the conductive line that are spaced apart from each other, a cathode electrode line that is electrically connected to the first via, an anode electrode line that is electrically connected to the second via, and a dummy pattern that is adjacent at least one of the cathode and anode electrode lines and electrically isolated from the conductive line.

16. 发明授权

US09466724B2 Semiconductor devices having source/drain and method of fabricating the same 有权
标题翻译：具有源极/漏极的半导体器件及其制造方法
公开(公告)号：US09466724B2
公开(公告)日：2016-10-11
申请号：US14704485
申请日：2015-05-05
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Changjae Yang , Shigenobu Maeda , Changhwa Kim , Youngmoon Choi
IPC分类号： H01L27/12 , H01L29/78 , H01L29/04
CPC分类号： H01L29/7853 , H01L29/045 , H01L29/41791 , H01L29/66545 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： According to an exemplary embodiment of the present embodiment, a semiconductor device is provided as follows. An active fin protrudes from a substrate, extending in a direction. A gate structure crosses a first region of the active fin. A source/drain is disposed on a second region of the active fin. The source/drain includes upper surfaces and vertical side surfaces. The vertical side surfaces are in substantially parallel with side surfaces of the active fin.
摘要翻译：根据本实施例的示例性实施例，提供如下的半导体器件。主动翅片从沿着方向延伸的基底突出。栅极结构与有源鳍片的第一区域交叉。源极/漏极设置在有源鳍片的第二区域上。源极/漏极包括上表面和垂直侧面。垂直侧表面基本上平行于活动翅片的侧表面。

17. 发明授权

US09093306B2 Low noise and high performance LSI device 有权
标题翻译：低噪声，高性能的LSI器件
公开(公告)号：US09093306B2
公开(公告)日：2015-07-28
申请号：US14337532
申请日：2014-07-22
申请人： Samsung Electronics Co., Ltd.
发明人： Shigenobu Maeda , Jeong Hwan Yang
IPC分类号： H01L29/94 , H01L29/76 , H01L27/092 , H01L21/8234 , H01L21/8238 , H01L27/105 , H01L29/66 , H01L29/78
CPC分类号： H01L27/0922 , H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L27/0207 , H01L27/092 , H01L27/1052 , H01L29/0649 , H01L29/665 , H01L29/7833 , H01L29/7842 , H01L29/7843 , H01L29/7845 , H01L29/7848
摘要： In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate. For example, mechanical stress can be applied to devices that operate in high-speed digital settings, while devices that operate in analog or RF signal settings, in which electrical noise such as flicker noise that may be introduced by applied stress may degrade performance, have no stress applied.
摘要翻译：在其中使用NMOS器件和PMOS器件的半导体器件中，以不同的模式（例如模拟和数字模式）来执行应力工程，根据所需的操作模式，对特定器件有选择地施加应力工程。也就是说，适当的机械应力，即拉伸或压缩，可以施加到和/或从设备（即，NMOS和/或PMOS器件）中去除和/或从器件去除，不仅基于它们的导电类型，即n型或p- 类型，而且还在于其预期的操作应用，例如模拟/数字，低电压/高电压，高速/低速，噪声敏感/噪声不敏感等。结果是个体的性能设备根据其运行模式进行优化。例如，机械应力可以应用于在高速数字设置中工作的设备，而在模拟或RF信号设置中工作的设备，其中可能由施加的应力引入的诸如闪烁噪声的电噪声可能降低性能，具有没有施加应力。

18. 发明授权

US11791184B2 Semiconductor fabrication process and method of optimizing the same 有权
公开(公告)号：US11791184B2
公开(公告)日：2023-10-17
申请号：US17719722
申请日：2022-04-13
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Jiho Kim , Minhyeok Kwon , Shigenobu Maeda , Jooyeok Seo , Minuk Lee
IPC分类号： H01L21/67 , G05B19/418
CPC分类号： H01L21/67276 , G05B19/41865 , G05B2219/32291 , G05B2219/33034 , G05B2219/45031
摘要： The program code, when executed by a processor, causes the processor to input fabrication data including a plurality of parameters associated with a semiconductor fabricating process to a framework to generate a first class for analyzing the fabrication data, to extract a first parameter targeted for analysis and a second parameter associated with the first parameter from the plurality of parameters and generate a second class for analyzing the first parameter as a sub class of the first class, to modify the first parameter and the second parameter into a data structure having a format appropriate to store in the second class, so as to be stored in the second class, to perform data analysis on the first parameter and the second parameter, to transform the first parameter and the second parameter into corresponding tensor data, and to input the tensor data to the machine learning model.

19. 发明授权

US11640797B2 Display driver IC for low voltage signal conversion and electronic device comprising the same 有权
公开(公告)号：US11640797B2
公开(公告)日：2023-05-02
申请号：US17215230
申请日：2021-03-29
申请人： Samsung Electronics Co., Ltd.
发明人： Shigenobu Maeda , Dong-Il Park
IPC分类号： G09G3/30 , G09G3/3291 , G09G3/3233 , G09G3/29 , H03K19/0185
摘要： A display driver integrated circuit (IC) is provided. The display driver IC includes a shift register configured to output a digital signal, and a digital-analog converter configured to receive the digital signal and generate a data voltage corresponding to the digital signal, wherein the digital-analog converter includes a delta-sigma modulator configured to output a modulated signal by receiving the digital signal and a first voltage, and performing delta-sigma modulation on the digital signal using the first voltage, and a level shifter configured to receive the modulated signal and a second voltage higher than the first voltage, and amplify the modulated signal using the second voltage.

20. 发明申请

US20230010252A1 SEMICONDUCTOR PROCESS MODELING SYSTEM AND METHOD 有权
公开(公告)号：US20230010252A1
公开(公告)日：2023-01-12
申请号：US17700825
申请日：2022-03-22
申请人： Samsung Electronics Co., Ltd.
发明人： Shigenobu Maeda , Wook Kim , Hongsik Kim , Heejun Kim , Seyoung Park , Seongjin Yoo , Minhong Yun , Daehan Han
IPC分类号： G06F30/398 , G06F30/27
摘要： Provided is a semiconductor process modeling system. The semiconductor process modeling system includes a preprocessing component configured to generate tensor data from raw data obtained from semiconductor manufacturing equipment, wherein, when the raw data is expressed as a raw matrix representing values of a plurality of process parameters for each of a plurality of wafers, at least one element of the raw matrix is omitted, when the tensor data is expressed as a tensor matrix representing values of a plurality of preprocessed process parameters for each of the plurality of wafers, the number of omitted elements of the tensor matrix is less than the number of omitted elements of the raw matrix, and the preprocessing component is configured to generate the tensor data by modifying the raw data based on at least one of characteristics of the semiconductor manufacturing equipment and characteristics of the plurality of process parameters.

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