会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 14. 发明授权
    • Multi-carrier wireless communication access terminal and data transmission method
    • 多载波无线通信接入终端和数据传输方式
    • US07672250B2
    • 2010-03-02
    • US11600360
    • 2006-11-15
    • Stanislaw CzajaMuhammad Afsar
    • Stanislaw CzajaMuhammad Afsar
    • G01R31/08G06F11/00G08C15/00H04J1/16H04J3/14H04L1/00H04L12/26
    • H04W28/18H04L1/1812H04L1/1822H04L5/0037H04W28/22H04W92/10
    • A method, apparatus, and system permits an access terminal (“AT”) for a multi-carrier CDMA wireless communication system to concurrently receive data on N different-frequency carriers while restricting one or more parameters that affect data reception rate, so that limited resources of the AT will be sufficient to properly process data packets on the N carriers. The data rate controlling parameter may be “I,” the number of supported H-ARQ channels for one or more of the N carriers. A relationship may be defined between the number of supported forward and/or reverse link carriers, versus the number of supported H-ARQ channels and/or other data rate controlling parameters. Messages may enable identification of AT characteristics, and configuration and/or dynamic re-configuration of AT data communication capabilities that are related to different values of N and corresponding different data rate controlling parameters.
    • 一种方法,装置和系统允许用于多载波CDMA无线通信系统的接入终端(“AT”)在限制影响数据接收速率的一个或多个参数的同时在N个不同频率载波上同时接收数据,使得有限 AT的资源将足以正确处理N个运营商的数据包。 数据速率控制参数可以是“I”,一个或多个N个载波的支持的H-ARQ信道的数量。 可以在所支持的正向和/或反向链路载波的数量与所支持的H-ARQ信道的数量和/或其他数据速率控制参数之间定义关系。 消息可以使得能够识别AT特性,以及与不同的N值和相应的不同数据速率控制参数相关的AT数据通信能力的配置和/或动态重新配置。
    • 15. 发明授权
    • Method and/or apparatus implemented in hardware to discard bad logical transmission units (LTUs)
    • 在硬件中实现的丢弃不良逻辑传输单元(LTU)的方法和/或装置
    • US07340667B2
    • 2008-03-04
    • US10842376
    • 2004-05-10
    • Alon SaadoMuhammad Afsar
    • Alon SaadoMuhammad Afsar
    • H03M13/00
    • H04L1/0052H04L1/0061
    • The present invention concerns an apparatus comprising a logic circuit, a compare circuit, a control circuit and a memory interface. The logic circuit may be configured to generate a check signal in response to (i) a data signal having a series of logical transmission units (LTUs) and (ii) a first control signal. The compare circuit may be configured to generate a compare signal in response to the check signal and the data signal. The control circuit configured to generate (i) the first control signal and (ii) a second control signal indicating a valid or invalid status of each of the LTUs, in response to a data valid signal and the compare signal. The memory interface may be configured to generate an output data signal in response to the second control signal. The memory interface is generally configured to store only the LTUs having a valid status.
    • 本发明涉及一种包括逻辑电路,比较电路,控制电路和存储器接口的装置。 逻辑电路可以被配置为响应于(i)具有一系列逻辑传输单元(LTU)的数据信号和(ii)第一控制信号而产生检查信号。 比较电路可以被配置为响应于检查信号和数据信号而产生比较信号。 所述控制电路经配置以响应于数据有效信号和所述比较信号产生(i)所述第一控制信号和(ii)指示每个所述LTU的有效或无效状态的第二控制信号。 存储器接口可以被配置为响应于第二控制信号而产生输出数据信号。 存储器接口通常被配置为仅存储具有有效状态的LTU。
    • 19. 发明申请
    • Multi-carrier wireless communication access terminal and data transmission method
    • 多载波无线通信接入终端和数据传输方式
    • US20070127516A1
    • 2007-06-07
    • US11600360
    • 2006-11-15
    • Stanislaw CzajaMuhammad Afsar
    • Stanislaw CzajaMuhammad Afsar
    • H04L12/413
    • H04W28/18H04L1/1812H04L1/1822H04L5/0037H04W28/22H04W92/10
    • A method, apparatus, and system permits an access terminal (“AT”) for a multi-carrier CDMA wireless communication system to concurrently receive data on N different-frequency carriers while restricting one or more parameters that affect data reception rate, so that limited resources of the AT will be sufficient to properly process data packets on the N carriers. The data rate controlling parameter may be “I,” the number of supported H-ARQ channels for one or more of the N carriers. A relationship may be defined between the number of supported forward and/or reverse link carriers, versus the number of supported H-ARQ channels and/or other data rate controlling parameters. Messages may enable identification of AT characteristics, and configuration and/or dynamic re-configuration of AT data communication capabilities that are related to different values of N and corresponding different data rate controlling parameters.
    • 一种方法,装置和系统允许用于多载波CDMA无线通信系统的接入终端(“AT”)在限制影响数据接收速率的一个或多个参数的同时在N个不同频率载波上同时接收数据,使得有限 AT的资源将足以正确处理N个运营商的数据包。 数据速率控制参数可以是“I”,一个或多个N个载波的支持的H-ARQ信道的数量。 可以在所支持的正向和/或反向链路载波的数量与所支持的H-ARQ信道的数量和/或其他数据速率控制参数之间定义关系。 消息可以使得能够识别AT特性,以及与不同的N值和相应的不同数据速率控制参数相关的AT数据通信能力的配置和/或动态重新配置。
    • 20. 发明授权
    • Method and system for efficient rename buffer deallocation within a
processor
    • 处理器内高效重命名缓冲区释放的方法和系统
    • US5765215A
    • 1998-06-09
    • US519556
    • 1995-08-25
    • Muhammad AfsarSoummya MallickRajesh B. Patel
    • Muhammad AfsarSoummya MallickRajesh B. Patel
    • G06F9/312G06F9/38G06F9/26G06F12/02
    • G06F9/30043G06F9/3836G06F9/384
    • A method and system are disclosed for managing the deallocation of a rename buffer allocated to an update instruction within a processor. The processor has a number of rename buffers for temporarily storing information associated with instructions executed by the processor, a number of registers, and a memory. According to the present invention, an update instruction is dispatched to the processor for execution. A particular rename buffer is then allocated to the update instruction. An effective address is generated for the update instruction, wherein the effective address specifies an address within the memory to be accessed by the update instruction. Next, the effective address is stored within the particular rename buffer. Prior to completion of the access to the effective address within memory, the effective address is transferred from the particular rename buffer to a particular one of the number of registers. Thereafter, the particular rename buffer is deallocated, wherein processor performance is enhanced by improved rename buffer availability.
    • 公开了一种用于管理分配给处理器内的更新指令的重命名缓冲器的分配的方法和系统。 处理器具有多个重命名缓冲器,用于临时存储与由处理器执行的指令相关联的信息,多个寄存器和存储器。 根据本发明,更新指令被发送到处理器执行。 然后将特定的重命名缓冲区分配给更新指令。 生成更新指令的有效地址,其中,有效地址指定要由更新指令访问的存储器内的地址。 接下来,有效地址存储在特定的重命名缓冲区内。 在访问存储器内的有效地址之前,将有效地址从特定重命名缓冲区传送到寄存器数目中的特定一个。 此后,取消分配特定重命名缓冲区,其中通过改进的重命名缓冲器可用性来增强处理器性能。