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11. 发明授权

US4338646A Current limiting circuit 失效
标题翻译：限流电路
公开(公告)号：US4338646A
公开(公告)日：1982-07-06
申请号：US257837
申请日：1981-04-27
申请人： William F. Davis , Robert N. Dotson
发明人： William F. Davis , Robert N. Dotson
IPC分类号： G05F1/573 , H02H9/02 , H02H3/08
CPC分类号： H02H9/02 , G05F1/573
摘要： A current limiting circuit is provided wherein the monitored voltage is applied to the base of first and second transistors, the first transistor having a substantially larger emitter area than the second transistor. Impedance means are connected to the emitters of the first and second transistors such that they function in conjunction with the emitter area ratio causing the current flowing through the first transistor to be higher than that flowing through the second transistor at low base voltages, while at higher base voltages the current flowing through the second transistor is higher than flowing through the first transistor. At some intermediate voltage the current flowing through both the first and second transistors is equal. This property may be used, for example, in a voltage regulator so as to divert base drive current from the output transistor at the point where the first and second currents are equal.
摘要翻译：提供了限流电路，其中所监测的电压被施加到第一和第二晶体管的基极，第一晶体管具有比第二晶体管大得多的发射极面积。阻抗装置连接到第一和第二晶体管的发射极，使得它们与发射极面积比一起起作用，使得流过第一晶体管的电流高于在低基极电压下流过第二晶体管的电流，而在较高的基极电压下基极电压流过第二晶体管的电流高于流经第一晶体管的电流。在一些中间电压下，流过第一和第二晶体管的电流相等。该属性可以用于例如电压调节器中，以便在第一和第二电流相等的点处将基极驱动电流从输出晶体管转移。

12. 发明授权

US06759891B2 Thermal shutdown circuit with hysteresis and method of using 有权
标题翻译：具有迟滞的热关断电路及其使用方法
公开(公告)号：US06759891B2
公开(公告)日：2004-07-06
申请号：US10133761
申请日：2002-04-29
申请人： Robert N. Dotson
发明人： Robert N. Dotson
IPC分类号： G05F326
CPC分类号： G01K7/01 , G01K3/005
摘要： An integrated circuit (10) includes a thermal shutdown circuit that incorporates hysteresis for shutting down a functional circuit (13) when its temperature exceeds a predefined value. First and second current sources (18, 17) respectively produce first and second reference currents (IREF1, IREF2) representative of first and second die temperatures of the integrated circuit. A current mirror (14) has an input (19) for summing the first and second reference currents and an output (15) for providing a mirror current (IMIRROR). A detection circuit (12) has an output coupled to the output of the current mirror for sinking the mirror current to produce a detection signal (VDET) as a function of the first and second die temperatures.
摘要翻译：集成电路（10）包括热关断电路，其在其功能电路（13）的温度超过预定值时包含用于关闭功能电路（13）的滞后。第一和第二电流源（18,17）分别产生表示集成电路的第一和第二管芯温度的第一和第二参考电流（IREF1，IREF2）。电流镜（14）具有用于对第一和第二参考电流求和的输入端（19）和用于提供反射镜电流（IMIRROR）的输出端（15）。检测电路（12）具有耦合到电流镜的输出的输出，用于吸收反射镜电流，以产生作为第一和第二裸片温度的函数的检测信号（VDET）。

13. 发明授权

US5258948A Memory cell sense technique 失效
标题翻译：记忆单元感应技术
公开(公告)号：US5258948A
公开(公告)日：1993-11-02
申请号：US829659
申请日：1992-02-03
申请人： Gary W. Hoshizaki , Robert N. Dotson
发明人： Gary W. Hoshizaki , Robert N. Dotson
IPC分类号： G11C7/06 , G11C11/409 , G11C11/419 , G11C11/00
CPC分类号： G11C11/419 , G11C7/062
摘要： A memory cell sense technique for sensing a logic state of a memory cell. An output level translator (33) which can be preset to a predetermined logic state is utilized. A current source circuit (24) and a current sink circuit (26) change memory cell sensing into two distinct modes. In the first mode, the memory cell logic state is identical to the preset output logic state. The memory cell generates a differential voltage which is countered by a differential voltage created by the current source and current sink circuit. Inputs to a sensing circuit common mode and non-complemented output (44) remains in the preset logic state. In the second mode, the current source circuit and current sink circuit aid the memory cell in generating a differential voltage. The sensing circuit senses the differential voltage and changes the non-complemented output (44) from the preset logic state.
摘要翻译：一种用于感测存储器单元的逻辑状态的存储单元检测技术。利用可以预设到预定逻辑状态的输出电平转换器（33）。电流源电路（24）和电流吸收电路（26）将存储器单元感测改变成两种不同的模式。在第一模式中，存储单元逻辑状态与预设的输出逻辑状态相同。存储单元产生由电流源和电流吸收电路产生的差分电压抵消的差分电压。感测电路公共模式和非补充输出（44）的输入保持在预设的逻辑状态。在第二模式中，电流源电路和电流吸收电路有助于存储单元产生差分电压。感测电路感测差分电压，并将非补充输出（44）从预设逻辑状态改变。

14. 发明授权

US4501979A Current amplifier having multiple selectable outputs 失效
标题翻译：电流放大器具有多个可选输出
公开(公告)号：US4501979A
公开(公告)日：1985-02-26
申请号：US413054
申请日：1982-08-30
申请人： Michael W. Null , Robert N. Dotson , Robert B. Davis
发明人： Michael W. Null , Robert N. Dotson , Robert B. Davis
IPC分类号： G05F3/26 , H03K17/62 , H03F3/04
CPC分类号： H03K17/6285 , G05F3/265
摘要： A current amplifier is provided having a single control amplifier and a plurality of output stages. The desired output stage is digitally selected. The ratios of the output stage currents may be selected during the metalization process. A single capacitor compensates for all output stages regardless of which output stage is selected.
摘要翻译：提供了具有单个控制放大器和多个输出级的电流放大器。所需的输出级数字选择。可以在金属化处理期间选择输出级电流的比率。单个电容器补偿所有输出级，无论选择哪个输出级。

15. 发明授权

US4461989A Voltage sense circuit for a bubble memory voltage booster 失效
标题翻译：用于气泡存储器电压增压器的电压检测电路
公开(公告)号：US4461989A
公开(公告)日：1984-07-24
申请号：US412069
申请日：1982-08-27
申请人： Robert N. Dotson , Robert B. Davies , Ira Miller
发明人： Robert N. Dotson , Robert B. Davies , Ira Miller
IPC分类号： G11C5/14 , G05F1/10 , G05F3/20
CPC分类号： G11C5/145
摘要： In a voltage boost circuit for use in conjunction with a bubble memory operational driver, an output transistor alternately turns on and off so as to permit current to flow through an inductor which, when terminated by turning off the output transistor, causes a high voltage to be built up across the inductor which causes charge to be transferred to and stored in a capacitor. The output transistor is not turned on again until the voltage across the inductor falls below a predetermined value. A current mirror circuit is coupled to the comparator input and includes a buffer transistor which, when the voltage at the comparator input exceeds the break-down voltage of the buffer transistor, acts as a BV.sub.ceo level shifter.
摘要翻译：在与气泡存储器操作驱动器结合使用的升压电路中，输出晶体管交替地导通和截止，以允许电流流过电感器，当通过关断输出晶体管而终止时，电感引起高电压在整个电感上形成电荷，使电荷转移并存储在电容器中。直到电感两端的电压下降到预定值以下，输出晶体管才再次导通。电流镜电路耦合到比较器输入，并且包括缓冲晶体管，当比较器输入端的电压超过缓冲晶体管的击穿电压时，缓冲晶体管充当BVceo电平移位器。

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