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11. 发明授权

US06426248B2 Process for forming power MOSFET device in float zone, non-epitaxial silicon 有权
标题翻译：在浮动区域形成功率MOSFET器件的工艺，非外延硅
公开(公告)号：US06426248B2
公开(公告)日：2002-07-30
申请号：US09734429
申请日：2000-12-11
申请人： Richard Francis , Chiu Ng
发明人： Richard Francis , Chiu Ng
IPC分类号： H01L21336
CPC分类号： H01L29/7802 , H01L29/1604 , H01L29/41766 , H01L29/456 , H01L29/66727
摘要： A vertical conduction MOSFET semiconductor device is formed in a non-epitaxial (float zone) lightly doped silicon substrate. Device junction regions are formed in the top surface of the lightly doped float zone substrate. The backside of the wafer is then ground by surface grinding to attain a desired thickness. Phosphorus, or another N type dopant species, is then implanted into the back surface and is activated by a laser anneal. Back surface damage caused by grinding and/or implantation is intentionally retained. Alternatively, a “transparent” layer is formed by depositing highly doped amorphous silicon on the back surface. Titanium, or another metal (excluding aluminum), is then deposited on the back surface and annealed to form a titanium silicide, or other silicide for a contact electrode.
摘要翻译：在非外延（浮动区）轻掺杂硅衬底中形成垂直导通MOSFET半导体器件。器件结区域形成在轻掺杂浮法区衬底的顶表面中。然后通过表面研磨将晶片的背面研磨以获得所需的厚度。然后将磷或另一种N型掺杂剂物质注入背表面，并通过激光退火来激活。故意保留由研磨和/或植入引起的背面损伤。或者，通过在后表面上沉积高度掺杂的非晶硅来形成“透明”层。然后将钛或另一种金属（不包括铝）沉积在背面上并退火以形成硅化钛或用于接触电极的其它硅化物。

12. 发明授权

US08314002B2 Semiconductor device having increased switching speed 有权
标题翻译：具有提高的开关速度的半导体器件
公开(公告)号：US08314002B2
公开(公告)日：2012-11-20
申请号：US11144727
申请日：2005-06-02
申请人： Richard Francis , Chiu Ng
发明人： Richard Francis , Chiu Ng
IPC分类号： H01L21/331
CPC分类号： H01L29/66333 , H01L29/0834 , H01L29/41741 , H01L29/456 , H01L29/7395
摘要： A semiconductor device is formed in a thin float zone wafer. Junctions are diffused into the top surface of the wafer and the wafer is then reduced in thickness by removal of material from its bottom surface. A weak collector is then formed in the bottom surface by diffusion of boron (for a P type collector). The weak collector is then formed or activated only over spaced or intermittent areas. This is done by implant of the collector impurity through a screening mask; or by activating only intermittent areas by a laser beam anneal in which the beam is directed to anneal only preselected areas. The resulting device has an effective very low implant dose, producing a reduced switching energy and increased switching speed, as compared to prior art weak collector/anodes and life time killing technologies.
摘要翻译：半导体器件形成在薄浮动区晶片中。结点扩散到晶片的顶表面，然后通过从其底表面去除材料来减小晶片的厚度。然后通过硼的扩散（用于P型收集器）在底表面中形成弱集电体。然后，弱集电器仅在间隔或间断区域形成或激活。这是通过通过掩模掩模注入收集器杂质完成的; 或者仅通过激光束退火仅激活间歇区域，其中光束被引导以退火仅预选区域。与现有技术的弱收集器/阳极和寿命杀死技术相比，所得到的器件具有有效的非常低的注入剂量，产生降低的开关能量和增加的开关速度。

13. 发明申请

US20070034941A1 Deep N diffusion for trench IGBT 审中-公开
标题翻译：沟槽IGBT的深N扩散
公开(公告)号：US20070034941A1
公开(公告)日：2007-02-15
申请号：US11204074
申请日：2005-08-15
申请人： Richard Francis , Chiu Ng
发明人： Richard Francis , Chiu Ng
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/66348 , H01L29/7397
摘要： An increased conductivity deep diffusion of the same conductivity type as that of the drift region is provided between adjacent trenches of a trench type IGBT and below the trenches to reduce the on resistance components of the drift region resistance and spreading resistance to current flow when the device is turned on. The deep diffusion has a higher concentration than that of the drift region, and has a width of from 4 to 10 microns. The wafer or die has a total width (or thickness) of about 70 to about 300 microns.
摘要翻译：在沟槽型IGBT的相邻沟槽之间并且在沟槽下方提供与漂移区相同的导电类型的增加的导电性深扩散，以减小漂移区电阻的导通电阻分量和当电流流动时对电流的扩散电阻打开深度扩散具有比漂移区更高的浓度，并且具有4至10微米的宽度。晶片或管芯具有约70至约300微米的总宽度（或厚度）。

14. 发明授权

US06753580B1 Diode with weak anode 有权
标题翻译：二极管与弱阳极
公开(公告)号：US06753580B1
公开(公告)日：2004-06-22
申请号：US09565148
申请日：2000-05-05
申请人： Richard Francis , Chiu Ng , Fabrizio Ruo Redda
发明人： Richard Francis , Chiu Ng , Fabrizio Ruo Redda
IPC分类号： H01L2976
CPC分类号： H01L29/66136 , H01L29/8611
摘要： A diode is formed having a weak injection shallow, low P concentration anode in an N type wafer or die. The resulting diode has a soft reverse recovery characteristic with low recovery voltage and is particularly useful either as a power factor correction diode or as an antiparallel connected diode in a motor control circuit.
摘要翻译：形成在N型晶片或裸片中具有弱注入浅，低P浓度阳极的二极管。所得二极管具有低的恢复电压的软反向恢复特性，并且在电动机控制电路中作为功率因数校正二极管或者作为反并联连接的二极管是特别有用的。

15. 发明授权

US06482681B1 Hydrogen implant for buffer zone of punch-through non epi IGBT 有权
标题翻译：用于穿通非外延IGBT缓冲区的氢注入
公开(公告)号：US06482681B1
公开(公告)日：2002-11-19
申请号：US09565922
申请日：2000-05-05
申请人： Richard Francis , Chiu Ng
发明人： Richard Francis , Chiu Ng
IPC分类号： H01L21332
CPC分类号： H01L29/456 , H01L21/26506 , H01L21/28512 , H01L29/1095 , H01L29/32 , H01L29/66333 , H01L29/7395 , H01L2924/0002 , H01L2924/00
摘要： An IGBT is formed in a thin (less than 250 microns thick) float zone silicon wafer using a hydrogen implant to form an N+ buffer layer at the bottom of the wafer. A weak anode is formed on the bottom of the wafer. A single hydrogen implant, or a plurality of hydrogen implants of progressively shallower depth and increasing dose can be used to form the implant in a diffused float zone wafer. The process may also be used to form an N+ contact region in silicon to permit a good ohmic contact to the silicon for any type device.
摘要翻译：使用氢注入在薄的（小于250微米厚）的浮动区硅晶片中形成IGBT，以在晶片的底部形成N +缓冲层。在晶片的底部形成弱阳极。可以使用单个氢植入物或逐渐变浅的深度和增加剂量的多个氢植入物在扩散的浮动区晶片中形成植入物。该工艺也可以用于在硅中形成N +接触区域，以允许任何类型的器件对硅进行良好的欧姆接触。

16. 发明授权

US06197649B1 Process for manufacturing planar fast recovery diode using reduced number of masking steps 有权
标题翻译：使用减少数量的掩模步骤制造平面快速恢复二极管的工艺
公开(公告)号：US06197649B1
公开(公告)日：2001-03-06
申请号：US09129165
申请日：1998-08-05
申请人： Richard Francis , Chiu Ng
发明人： Richard Francis , Chiu Ng
IPC分类号： H01L21331
CPC分类号： H01L29/66128
摘要： A fast recovery diode (FRED) is fabricated by a process using a reduced number of masking steps. The FRED is a vertical conduction device in which P type anode regions are isolated using either LOCOS oxidation or deposited low temperature oxide. The first masking step defines the anode and isolation regions, and a second masking step defines the aluminum contact layer. For devices having a breakdown voltage greater than 800 volts, a third masking step is included which defines the passivated area.
摘要翻译：通过使用减少数量的掩蔽步骤的工艺制造快速恢复二极管（FRED）。 FRED是垂直传导装置，其中使用LOCOS氧化或沉积的低温氧化物分离P型阳极区域。第一掩模步骤限定阳极和隔离区域，第二掩蔽步骤限定铝接触层。对于具有大于800伏的击穿电压的器件，包括限定钝化区域的第三掩蔽步骤。

17. 发明申请

US20070026577A1 High voltage non punch through IGBT for switch mode power supplies 有权
标题翻译：用于开关电源的高压非穿通IGBT
公开(公告)号：US20070026577A1
公开(公告)日：2007-02-01
申请号：US11190602
申请日：2005-07-27
申请人： Richard Francis , Chiu Ng
发明人： Richard Francis , Chiu Ng
IPC分类号： H01L21/332
CPC分类号： H01L29/7395 , H01L29/0834 , H01L29/41725 , H01L29/66333 , Y10S438/904
摘要： A process for forming an NPT IGBT in a thin N type silicon wafer in which the bottom surface of a thin silicon wafer (100 microns thick or less) has a shallow reduced lifetime region in its bottom formed by a light species atom implant to a depth of less than about 2.5 microns. A P+ transparent collector region about 0.5 microns deep is formed in the bottom of the damaged region by a boron implant. A collector contact of Al/Ti/NiV and Ag is sputtered onto the collector region and is annealed at 200° C. to 400° C. for 30 to 60 minutes. A pre-anneal step before applying the collector metal can be carried out in vacuum at 300° C. to 400° C. for 30 to 60 seconds.
摘要翻译：一种用于在薄N型硅晶片中形成NPT IGBT的工艺，其中薄硅晶片（100微米厚或更小）的底表面在其底部具有浅的减少的寿命区域，其通过光物质原子注入形成深度小于约2.5微米。通过硼注入在损伤区域的底部形成约0.5微米深的P + 将Al / Ti / NiV和Ag的集电极触点溅射到集电极区域，并在200℃至400℃退火30至60分钟。在施加集电体金属之前的预退火步骤可以在300℃至400℃的真空中进行30至60秒。

18. 发明申请

US20050227461A1 Semiconductor device having increased switching speed 有权
标题翻译：具有提高的开关速度的半导体器件
公开(公告)号：US20050227461A1
公开(公告)日：2005-10-13
申请号：US11144727
申请日：2005-06-02
申请人： Richard Francis , Chiu Ng
发明人： Richard Francis , Chiu Ng
IPC分类号： H01L21/331 , H01L29/08 , H01L29/417 , H01L29/45 , H01L29/739
CPC分类号： H01L29/66333 , H01L29/0834 , H01L29/41741 , H01L29/456 , H01L29/7395
摘要： A semiconductor device is formed in a thin float zone wafer. Junctions are diffused into the top surface of the wafer and the wafer is then reduced in thickness by removal of material from its bottom surface. A weak collector is then formed in the bottom surface by diffusion of boron (for a P type collector). The weak collector is then formed or activated only over spaced or intermittent areas. This is done by implant of the collector impurity through a screening mask; or by activating only intermittent areas by a laser beam anneal in which the beam is directed to anneal only preselected areas. The resulting device has an effective very low implant dose, producing a reduced switching energy and increased switching speed, as compared to prior art weak collector/anodes and life time killing technologies.
摘要翻译：半导体器件形成在薄浮动区晶片中。结点扩散到晶片的顶表面，然后通过从其底表面去除材料来减小晶片的厚度。然后通过硼的扩散（用于P型收集器）在底表面中形成弱集电体。然后，弱集电器仅在间隔或间断区域形成或激活。这是通过通过掩模掩模注入收集器杂质完成的; 或者仅通过激光束退火仅激活间歇区域，其中光束被引导以退火仅预选区域。与现有技术的弱收集器/阳极和寿命杀死技术相比，所得到的器件具有有效的非常低的注入剂量，产生降低的开关能量和增加的开关速度。

19. 发明授权

US06919248B2 Angled implant for shorter trench emitter 有权
标题翻译：用于短沟渠发射器的角度植入
公开(公告)号：US06919248B2
公开(公告)日：2005-07-19
申请号：US10389857
申请日：2003-03-14
申请人： Richard Francis , Chiu Ng
发明人： Richard Francis , Chiu Ng
IPC分类号： H01L21/265 , H01L21/331 , H01L21/336 , H01L29/08 , H01L29/739 , H01L29/78 , H01L31/062 , H01L21/425
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0839 , H01L29/0847 , H01L29/66348 , H01L29/7397
摘要： An insulated gate trench type semiconductor device having L-shaped diffused regions, each diffused region having a vertically oriented portion and a horizontally oriented portion extending laterally from the vertically oriented portion, and a method for manufacturing the device in which the vertically oriented portion of each L-shaped diffused region is formed by directing dopants at an angle toward a sidewall of a trench to form the vertically oriented portion using the edge of the opposing sidewall of the trench as a mask.
摘要翻译：一种具有L形扩散区域的绝缘栅沟槽型半导体器件，每个扩散区域具有垂直取向部分和从垂直取向部分横向延伸的水平取向部分，以及制造该器件的方法，其中每个通过使用沟槽的相对侧壁的边缘作为掩模将掺杂剂以一定角度引导到沟槽的侧壁以形成垂直取向的部分来形成L形扩散区域。

20. 发明授权

US06683331B2 Trench IGBT 有权
标题翻译：沟槽IGBT
公开(公告)号：US06683331B2
公开(公告)日：2004-01-27
申请号：US10132549
申请日：2002-04-25
申请人： Richard Francis , Chiu Ng
发明人： Richard Francis , Chiu Ng
IPC分类号： H01L2974
CPC分类号： H01L29/7397 , H01L29/0834 , H01L29/1095
摘要： An IGBT has parallel spaced trenches lined with gate oxide and filled with conductive polysilicon gate bodies. The trenches extend through a P− base region which is about 7 microns deep. A deep narrow N+ emitter diffusion is at the top of the trench and a shallow P+ contact diffusion extends between adjacent emitter diffusions. The N+ emitter diffusions are arranged to define a minimum RB′. The trenches are sufficiently deep to define long channel regions which can withstand a substantial portion of the blocking voltage of the device. A second blanket emitter implant and diffusion defines a shallow high concentration emitter diffusion extension at the top of the die for improved contact to the emitter diffusions.
摘要翻译： IGBT具有与栅极氧化物排列并且填充有导电多晶硅栅极体的平行隔开的沟槽。沟槽延伸穿过大约7微米深的P'基底区域。深沟N +发射体扩散在沟槽的顶部，浅的P +接触扩散在相邻的发射极扩散之间延伸。 N +发射极扩散布置成限定最小RB'。沟槽足够深以限定可以承受器件的大部分阻断电压的长通道区域。第二个覆盖发射器的注入和扩散在芯片的顶部限定了一个浅的高浓度发射极扩散延伸，以改善与发射极扩散的接触。

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