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11. 发明授权

US06828666B1 Low inductance power distribution system for an integrated circuit chip 失效
标题翻译：用于集成电路芯片的低电感配电系统
公开(公告)号：US06828666B1
公开(公告)日：2004-12-07
申请号：US09099758
申请日：1998-06-18
申请人： Dennis J. Herrell , Thomas P. Dolbear
发明人： Dennis J. Herrell , Thomas P. Dolbear
IPC分类号： H01L2352
CPC分类号： H05K1/0231 , H01L23/49827 , H01L23/49838 , H01L23/50 , H01L2224/16225 , H01L2924/00014 , H01L2924/01019 , H01L2924/15311 , H01L2924/19106 , H01L2924/3011 , H05K1/112 , H05K2201/10545 , H05K2201/10734 , H01L2224/0401
摘要： A low impedance electrical pathway from decoupling capacitance located on a circuit board to an integrated circuit chip. The integrated circuit includes multiple power and ground C4 bumps and is positioned on a first side of an integrated circuit carrier which is positioned on a first side of a circuit board. The integrated circuit carrier includes lateral conductors such as voltage and ground power planes. Power and ground carrier vias extend from the voltage and ground power planes, respectively, to the first side of the carrier, and power and ground subgroups of carrier vias extend from the voltage and ground power planes, respectively, to power and ground solder balls on a second side of the carrier. The circuit board includes power and ground plated through holes extending from contact pads on the first side of the circuit board to contact pads on a second side of the circuit board. Decoupling capacitors are positioned on the second side of the circuit board. The decoupling capacitors have positive and negative electrodes are electrically coupled to the power and ground plated through holes respectively. The C4 power and ground bumps, the power and ground carrier vias, the power and ground carrier via subgroups, the power and ground solder balls, the contact pads, the power and ground plated through holes, and the positive and negative electrodes are arranged in anti-parallel tessellations to reduce the inductance of a loop circuit from the decoupling capacitors to the integrated chip circuit.
摘要翻译：位于电路板上的去耦电容到集成电路芯片的低阻抗电路。集成电路包括多个电源和接地C4凸起，并且位于集成电路载体的位于电路板的第一侧上的第一侧上。集成电路载体包括诸如电压和接地电源平面的横向导体。电源和地面载体通孔分别从电压和接地电源平面延伸到载体的第一侧，载流子通孔的电源和接地子组分别从电压和接地电源平面延伸到电源和接地焊球上承运人的第二面。电路板包括从电路板的第一侧的接触焊盘延伸到电路板第二面上的接触焊盘的电源和接地电镀通孔。去耦电容器位于电路板的第二侧。去耦电容器具有正极和负极分别电耦合到电源和接地电镀通孔。 C4电源和接地突起，电源和接地载体通孔，电源和接地载体通过子组，电源和接地焊球，接触焊盘，电源和接地电镀通孔以及正极和负极布置在反平行镶嵌，以减少环路电路从去耦电容到集成芯片电路的电感。

12. 发明授权

US5926371A Heat transfer apparatus which accommodates elevational disparity across an upper surface of a surface-mounted semiconductor device 失效
标题翻译：传热装置，其适应横过表面安装半导体器件的上表面的高差
公开(公告)号：US5926371A
公开(公告)日：1999-07-20
申请号：US846001
申请日：1997-04-25
申请人： Thomas P. Dolbear
发明人： Thomas P. Dolbear
IPC分类号： H01L23/40 , H01L23/433 , H05K1/02 , H05K7/20
CPC分类号： H05K1/0204 , H01L23/4006 , H01L23/433 , H01L2023/4043 , H01L2023/4062 , H01L2023/4068 , H01L2023/4087 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2924/01012 , H01L2924/0102 , H01L2924/01046 , H01L2924/01055 , H01L2924/15311 , H01L2924/16152 , H01L2924/16251 , H05K1/0271 , H05K2201/10409 , H05K2201/10734 , H05K2201/2009 , H05K2203/1572
摘要： A heat transfer apparatus is presented accommodating elevational disparity of an upper surface of a semiconductor device with respect to the component side of a PCB without adversely affecting system reliability. The heat transfer apparatus includes a thermally conductive cap structure positioned between the semiconductor device and an ambient and thermally coupled to the semiconductor device. One embodiment includes one or more spacers which maintain a space between the cap structure and the semiconductor device. A chip mounted to the substrate of a ceramic BGA package is mechanically isolated from the cap structure by the spacers, preventing chip damage due to shock and vibration. A backing plate on a side of the PCB opposite the semiconductor device provides PCB structural support and additional heat transfer. Several fasteners attach the backing plate to the cap structure. A portion of the fasteners exert a force which urges the cap structure toward the semiconductor device, while the remainder of the fasteners fix the relative positions of the backing plate and the cap structure. Fixing the relative positions of the backing plate and the cap structure reduces creep problems and promotes stress relief in viscoplastic elements. A first thermal interface layer between the cap structure and the semiconductor device achieves an acceptably low thermal resistance value under a relatively small amount of pressure. The spacers are omitted in an alternate embodiment wherein the first thermal interface layer has a uniform thickness and a consistency which permits the thickness to be maintained during installation.
摘要翻译：本发明提供一种传热装置，其相对于PCB的组件侧适应半导体器件的上表面的高度差异，而不会不利地影响系统的可靠性。传热装置包括位于半导体器件和环境之间并热耦合到半导体器件的导热帽结构。一个实施例包括保持盖结构和半导体器件之间的空间的一个或多个间隔件。安装到陶瓷BGA封装的基板的芯片通过间隔物与盖结构机械隔离，防止由于冲击和振动引起的芯片损坏。在PCB的与半导体器件相对的一侧上的背板提供PCB结构支撑和额外的热传递。几个紧固件将背板连接到盖结构。紧固件的一部分施加一个推动帽结构朝向半导体器件的力，而其余的紧固件固定了背板和盖结构的相对位置。固定背板和盖结构的相对位置减少了蠕变问题，并促进了粘塑性元件的应力消除。帽结构和半导体器件之间的第一热界面层在相对较小的压力下实现可接受的低热阻值。在替代实施例中省略了间隔物，其中第一热界面层具有均匀的厚度和允许在安装期间保持厚度的稠度。

13. 发明授权

US08198723B1 Low inductance power distribution system for an integrated circuit chip 有权
标题翻译：用于集成电路芯片的低电感配电系统
公开(公告)号：US08198723B1
公开(公告)日：2012-06-12
申请号：US11003566
申请日：2004-12-03
申请人： Dennis J. Herrell , Thomas P. Dolbear
发明人： Dennis J. Herrell , Thomas P. Dolbear
IPC分类号： H01L23/52
CPC分类号： H05K1/0231 , H01L23/49827 , H01L23/49838 , H01L23/50 , H01L2224/16225 , H01L2924/00014 , H01L2924/01019 , H01L2924/15311 , H01L2924/19106 , H01L2924/3011 , H05K1/112 , H05K2201/10545 , H05K2201/10734 , H01L2224/0401
摘要： A low impedance electrical pathway from decoupling capacitance located on a circuit board to an integrated circuit chip. The integrated circuit includes multiple power and ground C4 bumps and is positioned on a first side of an integrated circuit carrier which is positioned on a first side of a circuit board. The integrated circuit carrier includes lateral conductors such as voltage and ground power planes. Power and ground carrier vias extend from the voltage and ground power planes, respectively, to the first side of the carrier, and power and ground subgroups of carrier vias extend from the voltage and ground power planes, respectively, to power and ground solder balls on a second side of the carrier. The circuit board includes power and ground plated through holes extending from contact pads on the first side of the circuit board to contact pads on a second side of the circuit board. Decoupling capacitors are positioned on the second side of the circuit board. The decoupling capacitors have positive and negative electrodes are electrically coupled to the power and ground plated through holes respectively. The C4 power and ground bumps, the power and ground carrier vias, the power and ground carrier via subgroups, the power and ground solder balls, the contact pads, the power and ground plated through holes, and the positive and negative electrodes are arranged in anti-parallel tessellations to reduce the inductance of a loop circuit from the decoupling capacitors to the integrated chip circuit.
摘要翻译：位于电路板上的去耦电容到集成电路芯片的低阻抗电路。集成电路包括多个电源和接地C4凸起，并且位于集成电路载体的位于电路板的第一侧上的第一侧上。集成电路载体包括诸如电压和接地电源平面的横向导体。电源和地面载体通孔分别从电压和接地电源平面延伸到载体的第一侧，载流子通孔的电源和接地子组分别从电压和接地电源平面延伸到电源和接地焊球上承运人的第二面。电路板包括从电路板的第一侧的接触焊盘延伸到电路板第二面上的接触焊盘的电源和接地电镀通孔。去耦电容器位于电路板的第二侧。去耦电容器具有正极和负极分别电耦合到电源和接地电镀通孔。 C4电源和接地突起，电源和接地载体通孔，电源和接地载体通过子组，电源和接地焊球，接触焊盘，电源和接地电镀通孔以及正极和负极布置在反平行镶嵌，以减少环路电路从去耦电容到集成芯片电路的电感。

14. 发明授权

US5963023A Power surge management for high performance integrated circuit 失效
标题翻译：电源浪涌管理用于高性能集成电路
公开(公告)号：US5963023A
公开(公告)日：1999-10-05
申请号：US99691
申请日：1998-06-18
申请人： Dennis James Herrell , Thomas P. Dolbear
发明人： Dennis James Herrell , Thomas P. Dolbear
IPC分类号： G05F3/24 , G06F1/30 , H01L23/498 , H01L23/50 , H02J1/02 , H05K1/11 , G05F1/40 , H03K17/12
CPC分类号： H01L23/49827 , G06F1/305 , H01L23/49838 , H01L23/50 , H02J1/02 , G05F3/24 , H01L2924/0002 , H01L2924/3011 , H05K1/112 , H05K2201/10545 , H05K2201/10734
摘要： An integrated circuit chip configuration, e.g., a microprocessor, includes feedback control circuitry defined thereon to control mid-frequency components of current demand of the integrated circuit chip and thereby regulate power supply voltage to within design tolerances of the integrated circuit chip. Such mid-frequency components can be generated by directed changes in operating frequency of the integrated circuit chip or by cyclic or episodic variations in circuit activity, e.g., instruction sequence dependent variations. When generated, such mid-frequency components can excite mid-frequency resonances in a power distribution system and generate power supply voltage disturbances. In some configurations, the integrated circuit chip includes current dump circuitry defining a controlled impedance path between first and second power supply voltage terminals of the integrated circuit chip. The controlled impedance path allows the feedback control circuitry to actuate a variable current draw so as to reduce mid-frequency components of overall current demand of the integrated circuit chip and thereby regulate power supply voltage disturbances. In other configurations, the feedback control circuitry is coupled to on-chip clock circuits, e.g., a phase-locked loop (PLL), to actuate variations in a clock signal supplied to the integrated circuit chip and thereby regulate power supply voltage disturbances.
摘要翻译：诸如微处理器的集成电路芯片配置包括在其上限定的反馈控制电路，以控制集成电路芯片的电流需求的中频分量，从而将电源电压调整到集成电路芯片的设计容限内。这样的中频分量可以通过集成电路芯片的工作频率的定向改变或电路活动中的循环或偶然变化（例如指令序列相关变化）来产生。当产生时，这种中频分量可以激发配电系统中的中频谐振并产生电源电压干扰。在一些配置中，集成电路芯片包括限定在集成电路芯片的第一和第二电源电压端子之间的受控阻抗路径的电流转储电路。受控阻抗路径允许反馈控制电路致动可变电流汲取，以减少集成电路芯片的总电流需求的中频分量，从而调节电源电压干扰。在其他配置中，反馈控制电路耦合到片上时钟电路，例如锁相环（PLL），以激励提供给集成电路芯片的时钟信号的变化，从而调节电源电压干扰。

15. 发明授权

US5907474A Low-profile heat transfer apparatus for a surface-mounted semiconductor device employing a ball grid array (BGA) device package 失效
标题翻译：用于采用球栅阵列（BGA）器件封装的表面安装半导体器件的低轮廓传热装置
公开(公告)号：US5907474A
公开(公告)日：1999-05-25
申请号：US845591
申请日：1997-04-25
申请人： Thomas P. Dolbear
发明人： Thomas P. Dolbear
IPC分类号： H01L23/04 , H01L23/40 , H01L23/433 , H05K1/02 , H05K3/32 , H05K3/34 , H05K7/10 , H05K7/20
CPC分类号： H01L24/32 , H01L23/04 , H01L23/4006 , H01L23/433 , H05K3/325 , H05K7/1061 , H01L2224/16 , H01L2224/27013 , H01L2224/73253 , H01L2224/83051 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01019 , H01L2924/0102 , H01L2924/01027 , H01L2924/01033 , H01L2924/01046 , H01L2924/01055 , H01L2924/01073 , H01L2924/01074 , H01L2924/01082 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/16152 , H01L2924/19041 , H05K1/0201 , H05K3/3436
摘要： A low-profile heat transfer apparatus is presented for a surface-mounted semiconductor device employing a ball grid array (BGA) device package having a chip mounted upon a substantially flat upper surface of a substrate. The semiconductor device is mounted upon a component side of a printed circuit board (PCB), and the heat transfer apparatus is used to transfer heat energy from the semiconductor device to an ambient. A thermally conductive cap structure is positioned between the semiconductor device and the ambient. The cap structure includes a bottom surface having a first cavity sized to receive the substrate and possibly any decoupling capacitors. During use, the substrate resides within the first cavity. In a first embodiment, the chip resides within a second cavity in an upper wall of the first cavity during use. The chip and substrate are thermally coupled to the cap structure by a first and second thermal interface layer, respectively. The use of two thermal interface layers achieves a relatively low value of .theta..sub.JS, allowing the cap structure to remain relatively small. In a second embodiment, the chip resides within a hole in the cap structure during use such that the upper surface of the chip is exposed to the ambient. The substrate is thermally coupled to the cap structure by a thermal interface layer. The achieved value of .theta..sub.JS is acceptably low for some applications, and the height of the cap structure relative to the component side of the PCB is substantially reduced.
摘要翻译：本发明提供了一种用于使用具有安装在基板的基本上平坦的上表面上的芯片的球栅阵列（BGA）器件封装的表面安装半导体器件的低调传热装置。半导体器件安装在印刷电路板（PCB）的组件侧，并且传热装置用于将热能从半导体器件传递到环境。导热盖结构位于半导体器件和环境之间。盖结构包括底表面，该底表面具有尺寸适于接纳衬底和可能的任何去耦电容器的第一腔。在使用期间，衬底位于第一腔内。在第一实施例中，在使用期间，芯片位于第一腔的上壁中的第二腔内。芯片和衬底分别通过第一和第二热界面层热耦合到盖结构。两个热界面层的使用实现了较低的θJS值，允许盖结构保持相对较小。在第二实施例中，在使用期间，芯片位于帽结构的孔内，使得芯片的上表面暴露于环境中。衬底通过热界面层热耦合到帽结构。对于一些应用，θJS的实现值是可接受的低，并且帽结构相对于PCB的部件侧的高度显着降低。

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