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11. 发明申请

US20060050561A1 Bitline governed approach for program control of non-volatile memory 有权
公开(公告)号：US20060050561A1
公开(公告)日：2006-03-09
申请号：US11207260
申请日：2005-08-18
申请人： Daniel Guterman , Nima Mokhlesi , Yupin Fong
发明人： Daniel Guterman , Nima Mokhlesi , Yupin Fong
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/12 , G11C16/30 , G11C16/3454 , G11C16/3459
摘要： In a system for programming non-volatile storage, technology is disclosed for programming with greater precision and reasonable program times. In one embodiment, a first voltage is applied to a bit line for a first non-volatile storage element in order to inhibit that first non-volatile storage element. A first program voltage is applied to the first non-volatile storage element. For example, a program pulse is applied to a control gate for the first non-volatile storage element. During the program pulse, the bit line is changed from said first voltage to a second voltage, where the second voltage allows the first non-volatile storage element to be programmed.

12. 发明申请

US20050248989A1 BITLINE GOVERNED APPROACH FOR PROGRAM CONTROL OF NON-VOLATILE MEMORY 有权
标题翻译：用于非易失性存储器的程序控制的双向管理方法
公开(公告)号：US20050248989A1
公开(公告)日：2005-11-10
申请号：US10839806
申请日：2004-05-05
申请人： Daniel Guterman , Nima Mokhlesi , Yupin Fong
发明人： Daniel Guterman , Nima Mokhlesi , Yupin Fong
IPC分类号： G11C11/34 , G11C16/04 , G11C16/12 , G11C16/30 , G11C16/34
CPC分类号： G11C16/0483 , G11C16/12 , G11C16/30 , G11C16/3454 , G11C16/3459
摘要： In a system for programming non-volatile storage, technology is disclosed for programming with greater precision and reasonable program times. In one embodiment, a first voltage is applied to a bit line for a first non-volatile storage element in order to inhibit that first non-volatile storage element. A first program voltage is applied to the first non-volatile storage element. For example, a program pulse is applied to a control gate for the first non-volatile storage element. During the program pulse, the bit line is changed from said first voltage to a second voltage, where the second voltage allows the first non-volatile storage element to be programmed.
摘要翻译：在用于编程非易失性存储器的系统中，公开了用于以更高的精度和合理的程序时间进行编程的技术。在一个实施例中，第一电压被施加到用于第一非易失性存储元件的位线，以便禁止第一非易失性存储元件。第一编程电压被施加到第一非易失性存储元件。例如，将编程脉冲施加到第一非易失性存储元件的控制栅极。在编程脉冲期间，位线从所述第一电压改变到第二电压，其中第二电压允许第一非易失性存储元件被编程。

13. 发明申请

US20050180211A1 Novel multi-state memory 有权
标题翻译：新型多状态存储器
公开(公告)号：US20050180211A1
公开(公告)日：2005-08-18
申请号：US11105855
申请日：2005-04-14
申请人： Daniel Guterman , Yupin Fong
发明人： Daniel Guterman , Yupin Fong
IPC分类号： G11C16/02 , G11C11/56 , G11C27/00 , H01L27/115 , H01L29/423 , H01L29/788 , G11C16/04
CPC分类号： H01L27/115 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0425 , G11C16/0441 , G11C16/28 , G11C16/3418 , G11C16/3427 , G11C16/349 , G11C16/3495 , G11C27/005 , G11C29/00 , G11C29/76 , G11C2211/5634 , H01L29/42324 , H01L29/42328 , H01L29/7885
摘要： Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.
摘要翻译：通过灵活，自我一致和自适应的检测方式实现了最大化的多状态压缩和更多的记忆状态容忍度，涵盖了广泛的动态范围。对于高密度多态编码，这种方法接近完全模拟处理，决定了模拟技术，包括A到D型转换，以重构和处理数据。根据本发明的教导，以高保真度读取存储器阵列，而不是提供实际的最终数字数据，而是提供准确地反映模拟存储状态的原始数据，哪些信息被发送到存储器控制器用于分析和检测实际的最终数字数据。

14. 发明申请

US20050057979A1 Noise reduction technique for transistors and small devices utilizing an episodic agitation 有权
公开(公告)号：US20050057979A1
公开(公告)日：2005-03-17
申请号：US10976692
申请日：2004-10-28
申请人： Nima Mokhlesi , Daniel Guterman , Geoffrey Gongwer
发明人： Nima Mokhlesi , Daniel Guterman , Geoffrey Gongwer
IPC分类号： G11C16/06 , G11C11/56 , G11C16/04 , G11C16/26 , G11C7/00
CPC分类号： G11C11/5642 , G11C16/0458 , G11C16/26
摘要： The present invention presents methods for reducing the amount of noise inherent in the reading of a non-volatile storage device by applying an episodic agitation (e.g. a time varying voltage) to some terminal(s) of the cell as part of the reading process. Various aspects of the present invention also extend to devices beyond non-volatile memories. According to one aspect of the present invention, in addition to the normal voltage levels applied to the cell as part of the reading process, a time varying voltage is applied to the cell. A set of exemplary embodiments apply a single or multiple set of alternating voltages to one or more terminals of a floating gate memory cell just prior to or during the signal integration time of a read process. In other embodiments, other reproducible external or internal agitations which are repeatable, and whose average effect (from one integration time to the next integration time) remains sufficiently constant so as to have a net noise reduction effect is applicable.

15. 发明申请

US20070109858A1 Novel Method and Structure for Efficient Data Verification Operation for Non-Volatile Memories 有权
标题翻译：用于非易失性存储器的高效数据验证操作的新方法和结构
公开(公告)号：US20070109858A1
公开(公告)日：2007-05-17
申请号：US11619991
申请日：2007-01-04
申请人： Kevin Conley , Daniel Guterman , Carlos Gonzales
发明人： Kevin Conley , Daniel Guterman , Carlos Gonzales
IPC分类号： G11C16/04
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C16/3454 , G11C2216/14
摘要： An improved flash EEPROM memory-based storage subsystem includes one or more flash memory arrays, each with three data registers and a controller circuit. During a flash program operation, one data register is used to control the program operation, a second register is used to hold the target data value, and a third register is used to load the next sector's data. Subsequent to a flash program operation, a sector's data are read from a flash array into the first data register and compared to the target data stored in the second register. When the data is verified good, the data from the third register is copied into the first and second registers for the next program operation. This creates an improved performance system that doesn't suffer data transfer latency during program operations that require data verification after the program operation is complete. Alternate embodiments perform the comparison using two register implementations and a single register implementations. The post-writer verification can be repeated and use different bias conditions for reading the data. The process can be automatic or executed by command that can specify the read conditions.
摘要翻译：改进的基于闪存EEPROM存储器的存储子系统包括一个或多个闪存阵列，每个闪存阵列具有三个数据寄存器和一个控制器电路。在闪存编程操作期间，使用一个数据寄存器来控制程序操作，第二个寄存器用于保存目标数据值，第三个寄存器用于加载下一个扇区的数据。在闪存编程操作之后，将扇区的数据从闪存阵列读入第一数据寄存器并与存储在第二寄存器中的目标数据进行比较。当数据验证良好时，来自第三寄存器的数据被复制到第一和第二寄存器用于下一个程序操作。这创建了一个改进的性能系统，在程序操作完成后需要数据验证的程序操作期间不会遭受数据传输延迟。替代实施例使用两个寄存器实现和单个寄存器实现来执行比较。可以重复写入后验证，并使用不同的偏置条件读取数据。该过程可以是自动的，也可以通过可以指定读取条件的命令执行。

16. 发明申请

US20070002633A1 Non-Volatile Memory with Improved Programming and Method Therefor 审中-公开
标题翻译：具有改进编程的非易失性存储器及其方法
公开(公告)号：US20070002633A1
公开(公告)日：2007-01-04
申请号：US11530818
申请日：2006-09-11
申请人： Geoffrey Gongwer , Daniel Guterman
发明人： Geoffrey Gongwer , Daniel Guterman
IPC分类号： G11C16/04
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C16/12 , G11C16/3454 , G11C16/3481 , G11C2211/5621
摘要： Non-volatile memory that has non-volatile charge storing capability such as EEPROM and flash EEPROM is programmed by a programming system that applies to a plurality of memory cells in parallel. Enhanced performance is achieved by programming each cell to its target state with a minimum of programming pulses using a data-dependent programming voltage. Further improvement is accomplished by performing the programming operation in multiphase where each successive phase is executed with a finer programming resolution such as employing a programming voltage with a gentler staircase waveform. These features allow rapid and accurate convergence to the target states for the group of memory cells being programmed in parallel, thereby allowing each cell to store several bits of information without sacrificing performance.
摘要翻译：具有诸如EEPROM和闪存EEPROM的非易失性电荷存储能力的非易失性存储器由并行应用于多个存储器单元的编程系统来编程。通过使用数据相关的编程电压以最小的编程脉冲将每个单元编程到其目标状态来实现增强的性能。通过执行多阶段中的编程操作来实现进一步的改进，其中每个连续相以更精细的编程分辨率执行，例如采用具有较温和的阶梯波形的编程电压。这些特征允许对并行编程的存储器单元组的目标状态进行快速和准确的收敛，从而允许每个单元存储几位信息而不牺牲性能。

17. 发明申请

US20060198192A1 Boosting to control programming of non-volatile memory 有权
公开(公告)号：US20060198192A1
公开(公告)日：2006-09-07
申请号：US11392901
申请日：2006-03-29
申请人： Daniel Guterman , Nima Mokhlesi , Yupin Fong
发明人： Daniel Guterman , Nima Mokhlesi , Yupin Fong
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/12 , G11C16/30 , G11C16/3418 , G11C16/3427 , G11C16/3454 , G11C16/3459
摘要： A system is disclosed for programming non-volatile memory with greater precision. In one embodiment, the system includes applying a first phase of a boosting signal to one or more unselected word lines for a set of NAND strings, applying a programming level to selected bit lines of the NAND strings while applying the first phase of the boosting signal, and applying an inhibit level to unselected bit lines of the NAND strings while applying the first phase of the boosting signal. Subsequently, a second phase of the boosting signal is applied to the one or more unselected word lines and the signal(s) on the selected bit lines are changed by applying the inhibit level to the selected bit lines so that NAND strings associated with the selected bit lines will be boosted by the second phase of the boosting signal. A program voltage signal is applied to a selected word line in order to program storage elements connected to the selected word line.

18. 发明申请

US20060107136A1 Smart verify for multi-state memories 有权
标题翻译：智能验证多状态存储器
公开(公告)号：US20060107136A1
公开(公告)日：2006-05-18
申请号：US11304961
申请日：2005-12-14
申请人： Geoffrey Gongwer , Daniel Guterman , Yupin Fong
发明人： Geoffrey Gongwer , Daniel Guterman , Yupin Fong
IPC分类号： G11C29/00
CPC分类号： G11C11/5635 , G11C11/5628 , G11C16/3454 , G11C16/3459 , G11C2211/5621
摘要： The present invention presents a “smart verify” technique whereby multi-state memories are programmed using a verify-results-based dynamic adjustment of the multi-states verify range for sequential-state-based verify implementations. This technique can increase multi-state write speed while maintaining reliable operation within sequentially verified, multi-state memory implementations. It does so by providing “intelligent” means to minimize the number of sequential verify operations for each program/verify/lockout step of the write sequence. In an exemplary embodiment of the write sequence for the multi-state memory during a program/verify cycle sequence of the selected storage elements, at the beginning of the process only the lowest state of the multi-state range to which the selected storage elements are being programmed is checked during the verify phase. Once the first storage state is reached by one or more of the selected elements, the next state in the sequence of multi-states is added to the verify process. This next state can either be added immediately upon the fastest elements reaching this preceding state in the sequence or after a delay of several program cycles. The adding of states to the set being checked in the verify phase continues through the rest of the set of multi-states in sequence, until the highest state has been added. Additionally, lower states can be removed from the verify set as all of the selected storage elements bound for these levels verify successfully to those target values and are locked out from further programming.
摘要翻译：本发明提出了一种“智能验证”技术，其中使用基于验证结果的动态调整多状态验证范围对基于顺序状态的验证实现进行多状态存储器的编程。这种技术可以提高多状态写入速度，同时在顺序验证的多状态存储器实现中保持可靠的操作。它通过提供“智能”手段来最小化写入序列的每个程序/验证/锁定步骤的顺序验证操作的数量。在所选择的存储元件的编程/验证周期序列期间用于多状态存储器的写入序列的示例性实施例中，在处理开始时，仅选择的存储元件的多状态范围的最低状态在验证阶段期间检查被编程。一旦所选元素中的一个或多个达到第一存储状态，则将多状态序列中的下一个状态添加到验证过程。这个下一个状态可以在序列中达到上述状态的最快的元素之后立即添加，或者在几个程序循环的延迟之后。在验证阶段中对被检查的集合中的状态的添加依次继续通过多个状态集合中的其余部分，直到添加了最高状态。另外，可以从验证集中删除较低的状态，因为为这些级别绑定的所有选定的存储元素成功验证到这些目标值，并被锁定进一步编程。

19. 发明申请

US20060067121A1 Variable current sinking for coarse/fine programming of non-volatile memory 有权
标题翻译：用于非易失性存储器粗/精编程的可变电流吸收
公开(公告)号：US20060067121A1
公开(公告)日：2006-03-30
申请号：US11280716
申请日：2005-11-16
申请人： Daniel Guterman , Nima Mokhlesi , Yupin Fong
发明人： Daniel Guterman , Nima Mokhlesi , Yupin Fong
IPC分类号： G11C16/06
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/3454 , G11C16/3481 , G11C27/005
摘要： A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory cells are verified for the fine programming process. The fine programming process can be accomplished using current sinking, charge packet metering or other suitable means.
摘要翻译：通过首先执行粗略编程处理并随后执行精细编程处理来编程非易失性存储器件。通过使用有效的验证方案来增强粗/精编程方法，该验证方案允许对粗略编程过程验证一些非易失性存储器单元，同时验证其它非易失性存储器单元用于精细编程过程。精细的编程过程可以使用电流吸收，电荷分组测量或其他合适的方法来完成。

20. 发明申请

US20060039198A1 Bitline governed approach for coarse/fine programming 有权
标题翻译：用于粗/精编程的位线控制方法
公开(公告)号：US20060039198A1
公开(公告)日：2006-02-23
申请号：US11207427
申请日：2005-08-18
申请人： Daniel Guterman , Nima Mokhlesi , Yupin Fong
发明人： Daniel Guterman , Nima Mokhlesi , Yupin Fong
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/12 , G11C16/30 , G11C16/3454 , G11C16/3459
摘要： In a system for programming non-volatile storage, technology is disclosed for programming with greater precision and reasonable program times. In one embodiment, a first voltage is applied to a bit line for a first non-volatile storage element in order to inhibit that first non-volatile storage element. A first program voltage is applied to the first non-volatile storage element. For example, a program pulse is applied to a control gate for the first non-volatile storage element. During the program pulse, the bit line is changed from said first voltage to a second voltage, where the second voltage allows the first non-volatile storage element to be programmed.
摘要翻译：在用于编程非易失性存储器的系统中，公开了用于以更高的精度和合理的程序时间进行编程的技术。在一个实施例中，第一电压被施加到用于第一非易失性存储元件的位线，以便禁止第一非易失性存储元件。第一编程电压被施加到第一非易失性存储元件。例如，将编程脉冲施加到第一非易失性存储元件的控制栅极。在编程脉冲期间，位线从所述第一电压改变到第二电压，其中第二电压允许第一非易失性存储元件被编程。

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