专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US08015526B2 Static timing slacks analysis and modification 有权
标题翻译：静态定时松散分析和修改
公开(公告)号：US08015526B2
公开(公告)日：2011-09-06
申请号：US12138871
申请日：2008-06-13
申请人： Thomas B. Chadwick, Jr. , Margaret R. Charlebois , David J. Hathaway , Jason E. Rotella , Douglas W. Stout , Ivan L. Wemple
发明人： Thomas B. Chadwick, Jr. , Margaret R. Charlebois , David J. Hathaway , Jason E. Rotella , Douglas W. Stout , Ivan L. Wemple
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method, system and computer program product for analyzing and modifying a static timing slack of a timing path in a static timing analysis of a design of an integrated circuit (IC) with a transient power supply are disclosed. A static timing slack analysis is performed at a selected endpoint in an IC to obtain a candidate timing path leading to the endpoint with a worst static timing slack. A transient static timing slack is determined for the candidate timing path for each clock cycle of a clock signal under the transient power supply. The determined transient static timing slack is used to adjust the timing of the IC and to modify the static timing slack of the candidate timing path.
摘要翻译：公开了一种用于在具有瞬态电源的集成电路（IC）的设计的静态时序分析中分析和修改定时路径的静态定时松弛的方法，系统和计算机程序产品。在IC中的选定端点处执行静态时序松弛分析，以获得以最差的静态时序松弛通向端点的候选定时路径。瞬态电源下的时钟信号的每个时钟周期的候选定时路径确定瞬态静态时序松弛。使用确定的瞬态静态时序松弛来调整IC的定时并修改候选定时路径的静态时序松弛。

12. 发明授权

US07890906B2 Method of laying out integrated circuit design based on known polysilicon perimeter densities of individual cells 有权
标题翻译：基于单个电池的已知多晶硅周边密度布置集成电路设计的方法
公开(公告)号：US07890906B2
公开(公告)日：2011-02-15
申请号：US12117761
申请日：2008-05-09
申请人： Laura S. Chadwick , James A. Culp , David J. Hathaway , Anthony D. Polson
发明人： Laura S. Chadwick , James A. Culp , David J. Hathaway , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Disclosed is a method of laying out individual cells of an integrated circuit design, based at least in part on the known polysilicon perimeter densities of those cells. That is, the method embodiments use the knowledge of polysilicon perimeter density for known cells to drive placement of those cells on a chip (i.e., to drive floor-planning). The method embodiments can be used to achieve approximately uniform across-chip polysilicon perimeter density and, thereby to limit performance parameter variations between functional devices that are attributable to variations in polysilicon perimeter density. Alternatively, the method embodiments can be used to selectively control variations in the average polysilicon perimeter density of different regions of a chip and, thereby to selectively control certain performance parameter variations between functional devices located in those different regions.
摘要翻译：公开了至少部分地基于这些单元的已知多晶硅周边密度来布置集成电路设计的单个单元的方法。也就是说，方法实施例使用已知单元的多晶硅周密度的知识来驱动这些单元在芯片上的放置（即，驱动楼层规划）。方法实施例可以用于实现大致均匀的跨芯片多晶硅周边密度，并且由此限制可归因于多晶硅周边密度变化的功能器件之间的性能参数变化。或者，方法实施例可以用于选择性地控制芯片的不同区域的平均多晶硅周长密度的变化，从而选择性地控制位于那些不同区域中的功能设备之间的某些性能参数变化。

13. 发明申请

US20100180244A1 Method For Efficiently Checkpointing And Restarting Static Timing Analysis Of An Integrated Circuit Chip 有权
标题翻译：有效地检查和重新启动集成电路芯片的静态时序分析的方法
公开(公告)号：US20100180244A1
公开(公告)日：2010-07-15
申请号：US12354360
申请日：2009-01-15
申请人： Kerim Kalafala , Hemlata Gupta , David J. Hathaway , Jeffrey G. Hemmett
发明人： Kerim Kalafala , Hemlata Gupta , David J. Hathaway , Jeffrey G. Hemmett
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method for loading checkpoint timing in an environment where the boundary arrival times, slews, required arrival times, or loads differ from the checkpoint run. A timing checkpoint file generated for one or more hierarchical modules, during which each input is assigned a unique phase tag. The association of unique phase tags allows subsequent restart analyses to efficiently adjust the checkpoint timing in relation to the restart timing environment. In the restart run, one or more such checkpoint files is read, during which an initial propagation of arrival, required arrivals and slew times are performed, followed by a local re-update based on adjusted arrival times and the required arrival times. Finally, if multiple hierarchical modules are updated, a global recalculation of timing values is performed based on a slack change threshold in order to determine whether any new timing failures have been introduced.
摘要翻译：在边界到达时间，转数，所需到达时间或负载与检查点运行不同的环境中加载检查点定时的方法。为一个或多个分层模块生成的定时检查点文件，在此期间为每个输入分配唯一的相位标签。独特相位标签的关联允许随后的重新启动分析以有效地调整与重启定时环境相关的检查点定时。在重新启动运行中，读取一个或多个这样的检查点文件，在此期间，执行到达的初始传播，所需到达和转换时间，然后基于调整的到达时间和所需的到达时间进行本地重新更新。最后，如果更新了多个分级模块，则基于松弛变化阈值执行定时值的全局重新计算，以便确定是否引入了任何新的定时故障。

14. 发明申请

US20090307645A1 METHOD AND SYSTEM FOR ANALYZING CROSS-TALK COUPLING NOISE EVENTS IN BLOCK-BASED STATISTICAL STATIC TIMING 有权
标题翻译：基于块状统计静态时序分析交叉口耦合噪声事件的方法与系统
公开(公告)号：US20090307645A1
公开(公告)日：2009-12-10
申请号：US12132636
申请日：2008-06-04
申请人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Gregory M. Schaeffer , Chandramouli Visweswariah
发明人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Gregory M. Schaeffer , Chandramouli Visweswariah
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/82
摘要： A method of performing statistical timing analysis of a logic design, including effects of signal coupling, includes performing a deterministic analysis to determine deterministic coupling information for at least one aggressor/victim net pair of the logic design. Additionally, the method includes performing a statistical timing analysis in which the deterministic coupling information for the at least one aggressor/victim net pair is combined with statistical values of the statistical timing analysis to determine a statistical effective capacitance of a victim of the aggressor/victim net pair. Furthermore, the method includes using the statistical effective capacitance to determine timing data used in the statistical timing analysis.
摘要翻译：执行包括信号耦合效应的逻辑设计的统计定时分析的方法包括执行确定性分析以确定逻辑设计的至少一个攻击者/受害者网对的确定性耦合信息。另外，该方法包括执行统计时序分析，其中至少一个攻击者/受害者网络对的确定性耦合信息与统计时间分析的统计值相结合，以确定攻击者/受害者的受害者的统计有效电容净对。此外，该方法包括使用统计有效电容来确定在统计时序分析中使用的定时数据。

15. 发明授权

US07469395B2 Wiring optimizations for power 有权
标题翻译：电力接线优化
公开(公告)号：US07469395B2
公开(公告)日：2008-12-23
申请号：US11952544
申请日：2007-12-07
申请人： John M. Cohn , Alvar A. Dean , Amir H. Farrahi , David J. Hathaway , Thomas M. Lepsic , Jagannathan Narasimhan , Scott A. Tetreault , Sebastian T. Ventrone
发明人： John M. Cohn , Alvar A. Dean , Amir H. Farrahi , David J. Hathaway , Thomas M. Lepsic , Jagannathan Narasimhan , Scott A. Tetreault , Sebastian T. Ventrone
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5022 , G06F17/5077
摘要： An electrical wiring structure and a computer system for designing the electrical wiring structure. The electrical wiring structure includes a wire pair. The wire pair includes a first wire and a second wire. The second wire is slated for being tri-stated. The wire pair has a same-direction switching probability φSD per clock cycle that is no less than a pre-selected minimum same-direction switching probability φSD,MIN or has an opposite-direction switching probability φOD per clock cycle that is no less than a pre-selected minimum opposite-direction switching probability φOD,MIN. The first wire and the second wire satisfies at least one mathematical relationship involving LCOMMON and WSPACING, where WSPACING is defined as a spacing between the first wire and the second wire, and LCOMMON is defined as a common run length of the first wire and the second wire.
摘要翻译：一种用于设计电气布线结构的电气布线结构和计算机系统。电气配线结构包括电线对。线对包括第一线和第二线。第二根电线被预定为三态。线对具有每时钟周期相同方向的切换概率phiSD，其不小于预先选择的最小相同方向切换概率phiSD，MIN或具有不小于a的每个时钟周期的相反方向切换概率phiOD 预先选择的最小相反方向切换概率phiOD，MIN。第一线和第二线满足涉及LCOMMON和WSPACING的至少一个数学关系，其中WSPACING被定义为第一线和第二线之间的间隔，并且LCOMMON被定义为第一线和第二线的公共行程长度线。

16. 发明授权

US07401307B2 Slack sensitivity to parameter variation based timing analysis 有权
标题翻译：对基于参数变化的时序分析的松弛敏感性
公开(公告)号：US07401307B2
公开(公告)日：2008-07-15
申请号：US10904309
申请日：2004-11-03
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Jeffrey H. Oppold , Anthony D. Polson
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Jeffrey H. Oppold , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.
摘要翻译：公开了一种用于改进IC设计的方法，系统和程序产品，其优先考虑根据其故障概率导致校正的松弛故障系数。通过确定的一组独立参数，当参数变化时，通过注意时序上的差异，通常在端点松弛时，对每个参数执行灵敏度分析。对于每个独立参数重复此步骤。然后从参考松弛和每个定时端点的松弛的灵敏度计算失效系数，并且确定至少一个定时端点是否失败阈值测试。然后将失败的定时终点根据其故障系数进行优先级修改。所需的总运行次数是一次运行，用作参考运行，每个参数再运行一次运行。

17. 发明授权

US07308669B2 Use of redundant routes to increase the yield and reliability of a VLSI layout 有权
标题翻译：使用冗余路由来提高VLSI布局的收益和可靠性
公开(公告)号：US07308669B2
公开(公告)日：2007-12-11
申请号：US10908593
申请日：2005-05-18
申请人： Markus T. Buehler , John M. Cohn , David J. Hathaway , Jason D. Hibbeler , Juergen Koehl
发明人： Markus T. Buehler , John M. Cohn , David J. Hathaway , Jason D. Hibbeler , Juergen Koehl
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5068
摘要： Disclosed is a method and system for inserting redundant paths into an integrated circuit. Particularly, the invention provides a method for identifying a single via in a first path connecting two elements, determining if an alternate route is available for connecting the two elements (other than a redundant via), and for inserting a second path into the available alternate route. The combination of the first and second paths provides greater redundancy than inserting a redundant via alone. More importantly, such redundant paths provide for redundancy when congestion prevents a redundant via from being inserted adjacent to the single via. An embodiment of the method further comprises removing the single via and any redundant wire segments, if all of the additional vias used to form the second path can be made redundant.
摘要翻译：公开了一种将冗余路径插入到集成电路中的方法和系统。特别地，本发明提供了一种用于在连接两个元件的第一路径中识别单个通孔的方法，确定替代路线是否可用于连接两个元件（不同于冗余通路），以及用于将第二路径插入到可用替代路线。第一和第二路径的组合提供了比单独插入冗余通道更大的冗余。更重要的是，当拥塞阻止冗余通道被插入邻近单个通道时，这种冗余路径提供了冗余。如果用于形成第二路径的所有附加通孔都可以是冗余的，则该方法的实施例还包括去除单个通孔和任何冗余线段。

18. 发明授权

US07010763B2 Method of optimizing and analyzing selected portions of a digital integrated circuit 有权
标题翻译：优化和分析数字集成电路的选定部分的方法
公开(公告)号：US07010763B2
公开(公告)日：2006-03-07
申请号：US10436213
申请日：2003-05-12
申请人： David J. Hathaway , Lawrence Kenneth Lange , Chandramouli Visweswariah , Patrick M. Williams
发明人： David J. Hathaway , Lawrence Kenneth Lange , Chandramouli Visweswariah , Patrick M. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Disclosed is a method for achieving timing closure in the design of a digital integrated circuit or system by selecting portions of the circuit or system to be optimized and portions of the circuit or system in which the effects of such optimization are to be analyzed during the optimization process. Optimized portions will include gates whose design parameters are to be changed, a first analyzed portion includes gates whose delays and edge slews are to be recomputed, and a second analyzed portion includes gates whose ATs and RATs are to be recomputed during optimization. Constraints are imposed at selected boundaries between these portions to prevent unwanted propagation of timing information and to ensure the validity of timing values used during optimization. Through this selection, the size of the problem posed to the underlying optimization method will be reduced, allowing larger circuits or systems to be optimized and allowing optimization to be performed more quickly.
摘要翻译：公开了一种在数字集成电路或系统的设计中实现定时闭合的方法，通过选择要优化的电路或系统的部分以及在优化期间分析这种优化的影响的电路或系统的部分处理。优化部分将包括其设计参数将被改变的门，第一分析部分包括要重新计算其延迟和边缘电压的门，并且第二分析部分包括在优化期间重新计算其AT和RAT的门。在这些部分之间的选定边界施加约束，以防止定时信息的不期望的传播，并确保优化期间使用的定时值的有效性。通过这种选择，将降低对基础优化方法造成的问题的大小，从而允许更大的电路或系统被优化，并允许更快地执行优化。

19. 发明授权

US06778999B2 Method for distributing a set of objects in computer application 失效
标题翻译：在计算机应用程序中分发一组对象的方法
公开(公告)号：US06778999B2
公开(公告)日：2004-08-17
申请号：US09976698
申请日：2001-10-12
申请人： David J. Hathaway
发明人： David J. Hathaway
IPC分类号： G06F1730
CPC分类号： G06F17/5072 , G06F17/5045 , Y10S707/959 , Y10S707/99944 , Y10S707/99945
摘要： A method of determining redistribution of objects among three or more containers in a network comprises determining an initial set of objects in each of the containers, identifying neighboring pairs of containers, determining a cost of moving objects between each of the neighboring pairs of containers, determining a desired change in occupancy of each container, and subsequently determining a desired total size of a set of objects to be moved between each identified neighboring pair of containers by solving a set of simultaneous linear equations. The objects are redistributed among the neighboring pairs of containers in accordance with the solution. The objects may be clock sinks and the containers clock nets on a chip, or the objects may be circuits to be placed in an integrated circuit and the containers regions of the chip, or the objects may be data files and the containers individual network server computers.
摘要翻译：确定网络中的三个或更多个容器之间的对象再分配的方法包括确定每个容器中的对象的初始集合，识别相邻的容器对，确定在每个相邻容器对之间移动对象的成本，确定每个容器的占有率的期望变化，并且随后通过求解一组联立线性方程来确定要在每个识别的相邻容器对之间移动的一组物体的期望总体尺寸。根据解决方案，对象在相邻的容器对之间重新分配。对象可以是时钟汇集器和芯片上的容器时钟网络，或者对象可以是被放置在集成电路中的电路，并且芯片的容器区域或对象可以是数据文件和容器单个网络服务器计算机。

20. 发明授权

US06651229B2 Generation of refined switching windows in static timing analysis 有权
标题翻译：在静态时序分析中生成精细的切换窗口
公开(公告)号：US06651229B2
公开(公告)日：2003-11-18
申请号：US09682707
申请日：2001-10-09
申请人： Robert J. Allen , Ravishankar Arunachalam , David J. Hathaway
发明人： Robert J. Allen , Ravishankar Arunachalam , David J. Hathaway
IPC分类号： G06F1750
CPC分类号： G06F17/5031
摘要： A method and structure to determine timing windows in a static timing analysis of an integrated circuit design, determines for at least one node in the integrated circuit design, an initial set of sub-windows and merges the sub-windows of the initial set into a final set of sub-windows.
摘要翻译：在集成电路设计的静态时序分析中确定定时窗口的方法和结构，为集成电路设计中的至少一个节点确定初始的子窗口集合并将初始集合的子窗口合并为最后一套子窗口。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式